#include "_cgo_export.h"

/* Test calling a Go function with multiple return values.  */

void
callMulti(void)
{
	struct multi_return result = multi();
	assert(strcmp(result.r0, "multi") == 0);
	assert(result.r1 == 0);
	free(result.r0);

	MTVSRQM R1, V1                          // 10340e42
	MTVSRWM R1, V1                          // 10320e42
	PADDI R3, $1234567890, $1, R4           // 06104996388302d2
	PADDI R0, $1234567890, $0, R4           // 06004996388002d2
	PADDI R0, $1234567890, $1, R4           // 06104996388002d2
	PDEPD R1, R2, R3                        // 7c231138
	PEXTD R1, R2, R3                        // 7c231178

	RXSBGT	$17, $8, $16, R9, R10 // eca991081057
	ROSBGT	$9, $24, $11, R11, R0 // ec0b89180b56
	RISBG	$0, $31, $32, R1, R2  // ec21001f2055
	RISBGN	$17, $8, $16, R3, R4  // ec4311081059
	RISBGZ	$9, $24, $11, R5, R6  // ec6509980b55
	RISBGNZ	$0, $31, $32, R7, R8  // ec87009f2059
	RISBHG	$17, $8, $16, R9, R10 // eca91108105d
	RISBLG	$9, $24, $11, R11, R0 // ec0b09180b51
	RISBHGZ	$17, $8, $16, R9, R10 // eca91188105d

	VREV16	V1.H4, V2.H4                                     // ERROR "invalid arrangement"
	FLDPQ	(R0), (R1, R2)                                   // ERROR "invalid register pair"
	FLDPQ	(R1), (F2, F2)                                   // ERROR "constrained unpredictable behavior"
	FSTPQ	(R1, R2), (R0)                                   // ERROR "invalid register pair"
	FLDPD	(R0), (R1, R2)                                   // ERROR "invalid register pair"

	}
}

func archArm() *Arch {
	register := make(map[string]int16)
	// Create maps for easy lookup of instruction names etc.
	// Note that there is no list of names as there is for x86.
	for i := arm.REG_R0; i < arm.REG_SPSR; i++ {
		register[obj.Rconv(i)] = int16(i)
	}
	// Avoid unintentionally clobbering g using R10.
	delete(register, "R10")
	register["g"] = arm.REG_R10
	for i := 0; i < 16; i++ {

-  ({ char __r0, __r1, __r2;						      \
-     (__builtin_constant_p (reject) && __string2_1bptr_p (reject)	      \
-      ? ((__r0 = ((const char *) (reject))[0], __r0 == '\0')		      \
-	 ? strlen (s)							      \
-	 : ((__r1 = ((const char *) (reject))[1], __r1 == '\0')		      \
-	    ? __strcspn_c1 (s, __r0)					      \
-	    : ((__r2 = ((const char *) (reject))[2], __r2 == '\0')	      \
-	       ? __strcspn_c2 (s, __r0, __r1)				      \

	switch name {
	case "F":
		if 0 <= n && n <= 31 {
			return arm64.REG_F0 + n, true
		}
	case "R":
		if 0 <= n && n <= 30 { // not 31
			return arm64.REG_R0 + n, true
		}
	case "V":
		if 0 <= n && n <= 31 {
			return arm64.REG_V0 + n, true
		}
	}
	return 0, false
}

// ARM64RegisterShift constructs an ARM64 register with shift operation.

		return 10
	}
	if name[0] != 'R' {
		p.errorf("expected g or R0 through R15; found %s", name)
		return 0
	}
	r, ok := p.registerReference(name)
	if !ok {
		return 0
	}
	reg := r - p.arch.Register["R0"]
	if reg < 0 {
		// Could happen for an architecture having other registers prefixed by R
		p.errorf("expected g or R0 through R15; found %s", name)
		return 0
	}
	return uint16(reg)
}

	case "FCR":
		if 0 <= n && n <= 31 {
			return mips.REG_FCR0 + n, true
		}
	case "M":
		if 0 <= n && n <= 31 {
			return mips.REG_M0 + n, true
		}
	case "R":
		if 0 <= n && n <= 31 {
			return mips.REG_R0 + n, true
		}
	case "W":
		if 0 <= n && n <= 31 {
			return mips.REG_W0 + n, true
		}
	}
	return 0, false

		if 0 <= n && n <= 31 {
			return loong64.REG_FCSR0 + n, true
		}
	case "FCC":
		if 0 <= n && n <= 31 {
			return loong64.REG_FCC0 + n, true
		}
	case "R":
		if 0 <= n && n <= 31 {
			return loong64.REG_R0 + n, true
		}
	}
	return 0, false