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Results 41 - 50 of 51 for ANDQ (0.07 sec)
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src/cmd/compile/internal/ssa/_gen/AMD64.rules
// Lowering shifts // Unsigned shifts need to return 0 if shift amount is >= width of shifted value. // result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff) (Lsh64x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMP(Q|L|W|B)const y [64]))) (Lsh32x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/internal/obj/x86/anames.go
"ADOXQ", "AESDEC", "AESDECLAST", "AESENC", "AESENCLAST", "AESIMC", "AESKEYGENASSIST", "ANDB", "ANDL", "ANDNL", "ANDNPD", "ANDNPS", "ANDNQ", "ANDPD", "ANDPS", "ANDQ", "ANDW", "ARPL", "BEXTRL", "BEXTRQ", "BLENDPD", "BLENDPS", "BLENDVPD", "BLENDVPS", "BLSIL", "BLSIQ", "BLSMSKL", "BLSMSKQ", "BLSRL", "BLSRQ", "BOUNDL", "BOUNDW",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 11 18:32:50 UTC 2023 - 19.1K bytes - Viewed (0) -
src/runtime/sys_dragonfly_amd64.s
MOVL $0xf1, 0xf1 // crash RET TEXT runtime·sigfwd(SB),NOSPLIT,$0-32 MOVQ fn+0(FP), AX MOVL sig+8(FP), DI MOVQ info+16(FP), SI MOVQ ctx+24(FP), DX MOVQ SP, BX // callee-saved ANDQ $~15, SP // alignment for x86_64 ABI CALL AX MOVQ BX, SP RET // Called using C ABI. TEXT runtime·sigtramp(SB),NOSPLIT|TOPFRAME|NOFRAME,$0 // Transition from C ABI to Go ABI. PUSH_REGS_HOST_TO_ABI0()
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jun 06 18:49:01 UTC 2023 - 8.3K bytes - Viewed (0) -
src/runtime/race_amd64.s
MOVQ g_m(R14), R13 // Switch to g0 stack. MOVQ SP, R12 // callee-saved, preserved across the CALL MOVQ m_g0(R13), R10 CMPQ R10, R14 JE call // already on g0 MOVQ (g_sched+gobuf_sp)(R10), SP call: ANDQ $~15, SP // alignment for gcc ABI CALL AX MOVQ R12, SP // Back to Go world, set special registers. // The g register (R14) is preserved in C. XORPS X15, X15 RET
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 18:37:29 UTC 2024 - 15.1K bytes - Viewed (0) -
src/crypto/internal/nistec/p256_asm_amd64.s
SBBQ $0, mul0 MOVQ acc4, acc0 MOVQ acc5, acc1 MOVQ acc6, acc2 MOVQ acc7, acc3 ADDQ $-1, acc4 ADCQ p256const0<>(SB), acc5 ADCQ $0, acc6 ADCQ p256const1<>(SB), acc7 ANDQ $1, mul0 CMOVQEQ acc0, acc4 CMOVQEQ acc1, acc5 CMOVQEQ acc2, acc6 CMOVQEQ acc3, acc7 RET /* ---------------------------------------*/ TEXT p256MulInternal(SB),NOSPLIT,$8
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 39.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc.s
ANDQ DX, (BX) // 482113 ANDQ R11, (BX) // 4c211b ANDQ DX, (R11) // 492113 ANDQ R11, (R11) // 4d211b ANDQ DX, DX // 4821d2 or 4823d2 ANDQ R11, DX // 4c21da or 4923d3 ANDQ DX, R11 // 4921d3 or 4c23da
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Oct 08 21:38:44 UTC 2021 - 581.9K bytes - Viewed (0) -
test/codegen/comparisons.go
// amd64:`TESTL`,-`ANDL` c0 := a&b < 0 // arm:`CMN`,-`ADD` // arm64:`CMNW`,-`ADD` c1 := a+b < 0 // arm:`TEQ`,-`XOR` c2 := a^b < 0 // arm64:`TST`,-`AND` // amd64:`TESTQ`,-`ANDQ` c3 := e&f < 0 // arm64:`CMN`,-`ADD` c4 := e+f < 0 // not optimized to single CMNW/CMN due to further use of b+d // arm64:`ADD`,-`CMNW` // arm:`ADD`,-`CMN` c5 := b+d == 0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 19 16:31:02 UTC 2024 - 15.2K bytes - Viewed (0) -
src/runtime/sys_openbsd_amd64.s
XORL AX, AX RET TEXT runtime·sigfwd(SB),NOSPLIT,$0-32 MOVQ fn+0(FP), AX MOVL sig+8(FP), DI MOVQ info+16(FP), SI MOVQ ctx+24(FP), DX MOVQ SP, BX // callee-saved ANDQ $~15, SP // alignment for x86_64 ABI CALL AX MOVQ BX, SP RET // Called using C ABI. TEXT runtime·sigtramp(SB),NOSPLIT|TOPFRAME|NOFRAME,$0 // Transition from C ABI to Go ABI. PUSH_REGS_HOST_TO_ABI0()
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jun 06 18:49:01 UTC 2023 - 15.5K bytes - Viewed (0) -
src/runtime/sys_darwin_amd64.s
CALL libc_kill(SB) RET TEXT runtime·sigfwd(SB),NOSPLIT,$0-32 MOVQ fn+0(FP), AX MOVL sig+8(FP), DI MOVQ info+16(FP), SI MOVQ ctx+24(FP), DX MOVQ SP, BX // callee-saved ANDQ $~15, SP // alignment for x86_64 ABI CALL AX MOVQ BX, SP RET // This is the function registered during sigaction and is invoked when // a signal is received. It just redirects to the Go function sigtrampgo.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Aug 03 16:07:59 UTC 2023 - 19.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteAMD64.go
v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ANDQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 712.7K bytes - Viewed (0)