AESE	V0.B16, V2.B16    // Use AES to compute the SBOX
		EORW	R13, R4
		LSLW	$1, R13           // Compute next Rcon
		ANDSW	$0x100, R13, ZR
		CSELW	NE, R14, R13, R13 // Fake modulo
		SUBS	$1, R8
		VMOV	V2.S[0], R0
		EORW	R0, R4
		EORW	R4, R5
		EORW	R5, R6
		EORW	R6, R7
		STPW.P	(R4, R5), 8(R10)
		STPW.P	(R6, R7), 8(R10)
	BNE	ks128Loop
	CBZ	R11, ksDone       // If dec is nil we are done

	MOVD	$-1, acc0
	MOVD	p256const0<>(SB), acc1
	MOVD	$0, acc2
	MOVD	p256const1<>(SB), acc3
	// Load the original value
	LDP	0*16(a_ptr), (t0, t1)
	LDP	1*16(a_ptr), (t2, t3)
	// Speculatively subtract
	SUBS	t0, acc0
	SBCS	t1, acc1
	SBCS	t2, acc2
	SBC	t3, acc3
	// If condition is 0, keep original value
	CMP	$0, hlp0
	CSEL	EQ, t0, acc0, acc0
	CSEL	EQ, t1, acc1, acc1
	CSEL	EQ, t2, acc2, acc2

	VLD1.P	64(R2), [V4.B16, V5.B16, V6.B16, V7.B16]
	VEOR	V0.B16, V4.B16, V4.B16
	VEOR	V1.B16, V5.B16, V5.B16
	VEOR	V2.B16, V6.B16, V6.B16
	VEOR	V3.B16, V7.B16, V7.B16
	VST1.P	[V4.B16, V5.B16, V6.B16, V7.B16], 64(R0)
	SUBS	$64, R3
	CMP	$64, R3
	BGE	loop_64
tail:
	// quick end
	CBZ	R3, end
	TBZ	$5, R3, less_than32
	VLD1.P	32(R1), [V0.B16, V1.B16]
	VLD1.P	32(R2), [V2.B16, V3.B16]
	VEOR	V0.B16, V2.B16, V2.B16

	SUBSW R2.SXTH<<3, R13, R6                  // a6ad226b
	SUBS R21.UXTX<<2, R27, R4                  // 646b35eb
	SUBSW $(44<<12), R6, R9                    // SUBSW $180224, R6, R9         // c9b04071
	SUBS $(1804<<12), R13, R9                  // SUBS $7389184, R13, R9        // a9315cf1
	SUBSW R22->28, R6, R7                      // c770966b
	SUBSW R22>>28, R6, R7                      // c770566b
	SUBS R26<<15, R6, R16                      // d03c1aeb

	for i > 0 && p.stack[i-1].Op < opPseudo {
		i--
	}
	subs := p.stack[i:]
	p.stack = p.stack[:i]

	// Make sure top class is clean.
	// All the others already are (see swapVerticalBar).
	if len(subs) > 0 {
		cleanAlt(subs[len(subs)-1])
	}

	// Empty alternate is special case
	// (shouldn't happen but easy to handle).
	if len(subs) == 0 {
		return p.push(p.newRegexp(OpNoMatch))
	}

	// Test that ReadDir uses Open when the method is not present.
	dirs, err = ReadDir(openOnly{testFsys}, ".")
	check("openOnly", dirs, err)

	// Test that ReadDir on Sub of . works (sub_test checks non-trivial subs).
	sub, err := Sub(testFsys, ".")
	if err != nil {
		t.Fatal(err)
	}
	dirs, err = ReadDir(sub, ".")
	check("sub(.)", dirs, err)
}

func TestFileInfoToDirEntry(t *testing.T) {
	testFs := fstest.MapFS{

	SUBS	$0xff, R6, RSP                                   // ERROR "illegal destination register"
	SUBS	$0xffff0, R6, RSP                                // ERROR "illegal destination register"
	SUBS	$0x1000100010001000, R6, RSP                     // ERROR "illegal destination register"
	SUBS	$0x10001000100011, R6, RSP                       // ERROR "illegal destination register"

    return scope.status();
  }

  std::vector<absl::string_view> subs = absl::StrSplit(input_subs, ',');
  if (subs.size() != 2) {
    return errors::InvalidArgument("Only 2 inputs are supported");
  }
  std::string x_subs(subs[0]);
  std::string y_subs(subs[1]);
  // Add ellipsis for broadcasted dimensions if any operand does not have it.

	"FNEG",
	"FNEGCC",
	"FNMADD",
	"FNMADDCC",
	"FNMADDS",
	"FNMADDSCC",
	"FNMSUB",
	"FNMSUBCC",
	"FNMSUBS",
	"FNMSUBSCC",
	"FRSP",
	"FRSPCC",
	"FSUB",
	"FSUBCC",
	"FSUBS",
	"FSUBSCC",
	"ISEL",
	"MOVMW",
	"LBAR",
	"LHAR",
	"LSW",
	"LWAR",
	"LWSYNC",
	"MOVDBR",
	"MOVWBR",
	"MOVB",
	"MOVBU",
	"MOVBZ",
	"MOVBZU",
	"MOVH",
	"MOVHBR",

The anatomy of a typical project root directory looks as follows:

[listing,subs=+macros]
----
├── .gradle                 // <1>
│   ├── 4.8                     // <2>
│   ├── 4.9                     // <2>
│   └── ⋮
├── build                   // <3>
├── gradle