XORL    g, y2;                       \ // y2 = CH = ((f^g)&e)^g		// CH
	;                                    \
	VPXOR   XTMP2, XTMP3, XTMP3;         \ // XTMP3 = W[-15] ror 7 ^ W[-15] ror 18
	XORL    T1, y1;                      \ // y1 = (a>>22) ^ (a>>13) ^ (a>>2)		// S0
	MOVL    a, T1;                       \ // T1 = a						// MAJB
	ANDL    c, T1;                       \ // T1 = a&c						// MAJB

	return bits.RotateLeft8(n, s)
}

func RotateLeftVariable(n uint, m int) uint {
	// amd64:"ROLQ"
	// arm64:"ROR"
	// ppc64x:"ROTL"
	// s390x:"RLLG"
	// wasm:"I64Rotl"
	return bits.RotateLeft(n, m)
}

func RotateLeftVariable64(n uint64, m int) uint64 {
	// amd64:"ROLQ"
	// arm64:"ROR"
	// ppc64x:"ROTL"
	// s390x:"RLLG"
	// wasm:"I64Rotl"
	return bits.RotateLeft64(n, m)
}

	case sxtw:
		return "SXTW"

	case sxtx:
		return "SXTX"

	case lsl:
		return "LSL"

	case lsr:
		return "LSR"

	case asr:
		return "ASR"

	case ror:
		return "ROR"
	}
	return ""
}

type RegExtshiftAmount struct {
	reg       Reg
	extShift  ExtShift
	amount    uint8
	show_zero bool
}

func (RegExtshiftAmount) isArg() {}

	OR:        true,
	OUT:       true,
	POP:       true,
	POPA:      true,
	POPCNT:    true,
	PUSH:      true,
	PUSHA:     true,
	RCL:       true,
	RCR:       true,
	ROL:       true,
	ROR:       true,
	SAR:       true,
	SBB:       true,
	SHL:       true,
	SHLD:      true,
	SHR:       true,
	SHRD:      true,
	SUB:       true,
	TEST:      true,
	XADD:      true,
	XCHG:      true,

	RotateRight      Shift = 3 // right rotate
	RotateRightExt   Shift = 4 // right rotate through carry (Count will always be 1)
)

var shiftName = [...]string{
	"LSL", "LSR", "ASR", "ROR", "RRX",
}

func (s Shift) String() string {
	if s < 5 {
		return shiftName[s]
	}
	return fmt.Sprintf("Shift(%d)", int(s))
}

// A RegShift is a register shifted by a constant.

	{0xffffffff, 0xd69f03e0, ERET, instArgs{}, nil},
	// ROR <Wd>, <Ws>, #<shift>
	{0xffe08000, 0x13800000, ROR, instArgs{arg_Wd, arg_Ws, arg_immediate_0_31_imms}, ror_extr_32_extract_cond},
	// EXTR <Wd>, <Wn>, <Wm>, #<lsb>
	{0xffe08000, 0x13800000, EXTR, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_immediate_0_31_imms}, nil},
	// ROR <Xd>, <Xs>, #<shift>

	ADDW $1864, R25, R6           <=>    add w6, w25, #0x748

Optionally-shifted registers are written as <Rm>{<shift><amount>}.
The <shift> can be <<(lsl), >>(lsr), ->(asr), @>(ror).

Examples:

	ADD R19>>30, R10, R24     <=>    add x24, x10, x19, lsr #30
	ADDW R26->24, R21, R15    <=>    add w15, w21, w26, asr #24

Extended registers are written as <Rm>{.<extend>{<<<amount>}}.

		{name: "ROLW", argLength: 2, reg: gp21, asm: "ROLW"},                  // rotate left least significant word of arg0 by (arg1 & 31), sign extended
		{name: "ROR", argLength: 2, reg: gp21, asm: "ROR"},                    // rotate right arg0 by (arg1 & 63)
		{name: "RORI", argLength: 1, reg: gp11, asm: "RORI", aux: "Int64"},    // rotate right arg0 by auxint, shift amount 0-63

	/*10550*/ uint16(xSetOp), uint16(ROR),
	/*10552*/ uint16(xReadIb),
	/*10553*/ uint16(xArgRM16),
	/*10554*/ uint16(xArgImm8u),
	/*10555*/ uint16(xMatch),
	/*10556*/ uint16(xSetOp), uint16(ROR),
	/*10558*/ uint16(xReadIb),
	/*10559*/ uint16(xArgRM32),
	/*10560*/ uint16(xArgImm8u),
	/*10561*/ uint16(xMatch),
	/*10562*/ uint16(xSetOp), uint16(ROR),
	/*10564*/ uint16(xReadIb),

	r := immr & levels
	esize = 1 << length
	if esize > datasize {
		return nil
	}
	welem = 1<<(s+1) - 1
	ror := (welem >> r) | (welem << (esize - r))
	ror &= ((1 << esize) - 1)
	wmask = 0
	for i = 0; i < datasize; i += esize {
		wmask = (wmask << esize) | ror
	}
	return Imm64{wmask, false}