VCMEQ	V1.D2, V5.D2, V9.D2
	VCMEQ	V2.D2, V6.D2, V10.D2
	VCMEQ	V3.D2, V7.D2, V11.D2
	VAND	V8.B16, V9.B16, V8.B16
	VAND	V8.B16, V10.B16, V8.B16
	VAND	V8.B16, V11.B16, V8.B16
	CMP	R0, R6
	VMOV	V8.D[0], R4
	VMOV	V8.D[1], R5
	CBZ	R4, not_equal
	CBZ	R5, not_equal
	BNE	chunk64_loop
	AND	$0x3f, R2, R2
	CBZ	R2, equal
chunk16:
	// work with 16-byte chunks
	BIC	$0xf, R2, R3
	CBZ	R3, tail

	VMOV V18.B[10], V27                                         // 5b06155e
	VDUP V18.B[10], V27                                         // 5b06155e
	VMOV V12.B[2], V28.B[12]                                    // 9c15196e
	VMOV R30, V4.B[13]                                          // c41f1b4e
	VMOV V2.B16, V4.B16                                         // 441ca24e

	{VCMP_E_EQ_F64, []int{1, 0}, "VCMP.E", "CMPD"},
	{VLDR_EQ, []int{1}, "VLDR", "MOV"},
	{VSTR_EQ, []int{1}, "VSTR", "MOV"},
	{VMOV_EQ_F32, []int{1, 0}, "VMOV", "MOVF"},
	{VMOV_EQ_F64, []int{1, 0}, "VMOV", "MOVD"},
	{VMOV_EQ_32, []int{1, 0}, "VMOV", "MOVW"},
	{VMOV_EQ, []int{1, 0}, "VMOV", "MOVW"},
	{VCVT_EQ_F64_F32, []int{1, 0}, "VCVT", "MOVFD"},
	{VCVT_EQ_F32_F64, []int{1, 0}, "VCVT", "MOVDF"},

	rounds12to59	(m0,4,m3,m1,sha256msg1,vmov)    // 16-19
	rounds12to59	(m1,5,m0,m2,sha256msg1,vmov)    // 20-23
	rounds12to59	(m2,6,m1,m3,sha256msg1,vmov)    // 24-27
	rounds12to59	(m3,7,m2,m0,sha256msg1,vmov)    // 28-31
	rounds12to59	(m0,8,m3,m1,sha256msg1,vmov)    // 32-35
	rounds12to59	(m1,9,m0,m2,sha256msg1,vmov)    // 36-39
	rounds12to59	(m2,10,m1,m3,sha256msg1,vmov)   // 40-43

related to real ARM64 instruction. NOOP serves for the hardware nop instruction. NOOP is an alias of
HINT $0.

Examples:

	VMOV V13.B[1], R20      <=>      mov x20, v13.b[1]
	VMOV V13.H[1], R20      <=>      mov w20, v13.h[1]
	JMP (R3)                <=>      br x3
	CALL (R17)              <=>      blr x17
	LDAXRB (R19), R16       <=>      ldaxrb w16, [x19]
	NOOP                    <=>      nop

# Register mapping rules

	FMOVD	F4, (R2)(R6<<3)                 // 447826fc

// vmov
	VMOV	V8.S[1], R1           // 013d0c0e
	VMOV	V0.D[0], R11          // 0b3c084e
	VMOV	V0.D[1], R11          // 0b3c184e
	VMOV	R20, V1.S[0]          // 811e044e
	VMOV	R20, V1.S[1]          // 811e0c4e
	VMOV	R1, V9.H4             // 290c020e
	VDUP	R1, V9.H4             // 290c020e
	VMOV	R22, V11.D2           // cb0e084e
	VDUP	R22, V11.D2           // cb0e084e

	CBZ	R10, noaes
	MOVD	$runtime·aeskeysched+0(SB), R3

	VEOR	V0.B16, V0.B16, V0.B16
	VLD1	(R3), [V2.B16]
	VLD1	(R0), V0.S[1]
	VMOV	R1, V0.S[0]

	AESE	V2.B16, V0.B16
	AESMC	V0.B16, V0.B16
	AESE	V2.B16, V0.B16
	AESMC	V0.B16, V0.B16
	AESE	V2.B16, V0.B16

	VMOV	V0.D[0], R0
	RET
noaes:
	B	runtime·memhash32Fallback<ABIInternal>(SB)

// func memhash64(p unsafe.Pointer, h uintptr) uintptr

		o1 |= ((uint32(p.Scond) & C_SCOND) ^ C_SCOND_XOR) << 28

	case 80: /* fmov zfcon,freg */
		if p.As == AMOVD {
			o1 = 0xeeb00b00 // VMOV imm 64
			o2 = c.oprrr(p, ASUBD, int(p.Scond))
		} else {
			o1 = 0x0eb00a00 // VMOV imm 32
			o2 = c.oprrr(p, ASUBF, int(p.Scond))
		}

		v := int32(0x70) // 1.0
		r := (int(p.To.Reg) & 15) << 0

		// movf $1.0, r

			}
			size = 0
			Q = 0
		}

		o1 |= (uint32(Q&1) << 30) | (uint32(size&3) << 22) | (uint32(rf&31) << 16) | (uint32(r&31) << 5) | uint32(rt&31)

	case 73: /* vmov V.<T>[index], R */
		rf := int(p.From.Reg)
		rt := int(p.To.Reg)
		imm5 := 0
		o1 = 7<<25 | 0xf<<10
		index := int(p.From.Index)
		switch (p.From.Reg >> 5) & 15 {
		case ARNG_B:

		rel := obj.Addrel(c.cursym)
		rel.Off = int32(c.pc + 4)
		rel.Siz = 4
		rel.Sym = p.From.Sym
		rel.Add = p.From.Offset
		rel.Type = objabi.R_ADDRMIPSTLS

	case 56: /* vmov{b,h,w,d} $scon, wr */

		v := c.regoff(&p.From)
		o1 = OP_VI10(110, c.twobitdf(p.As), v, uint32(p.To.Reg), 7)

	case 57: /* vld $soreg, wr */
		v := c.lsoffset(p.As, c.regoff(&p.From))