//	LMOVW mreg ',' rreg
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	MOVW	M1, R1 // 40010800
	MOVV	M1, R1 // 40210800


//
// integer operations
// logical instructions
// shift instructions
// unary instructions
//
//	LADDW rreg ',' sreg ',' rreg
//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	ADD	R5, R9, R10	// 01255020
	ADDU	R13, R14, R19	// 01cd9821

	ORW	-1(R1), R2            // e3201fffff56
	XOR	(R1), R2              // e32010000082
	XORW	(R1), R2              // 57201000
	XORW	-1(R1), R2            // e3201fffff57

	// shift and rotate instructions
	SRD	$4, R4, R7              // eb740004000c
	SRD	R1, R4, R7              // eb741000000c
	SRW	$4, R4, R7              // eb74000400de
	SRW	R1, R4, R7              // eb74100000de

	SHA256RNDS2 X0, (BX), X11  // 440f38cb1b
	SHA256RNDS2 X0, (R11), X11 // 450f38cb1b
	SHA256RNDS2 X0, X2, X11    // 440f38cbda
	SHA256RNDS2 X0, X11, X11   // 450f38cbdb
	// Rest SHA instructions tests.
	SHA1MSG1 (BX), X2        // 0f38c913
	SHA1MSG1 (R11), X2       // 410f38c913
	SHA1MSG1 X2, X2          // 0f38c9d2
	SHA1MSG1 X11, X2         // 410f38c9d3
	SHA1MSG1 (BX), X11       // 440f38c91b

// available in cmd/internal/obj/ppc64/asm9.go with
// their valid instruction encodings.

#include "../../../../../runtime/textflag.h"

// In case of index mode instructions, usage of
// (Rx)(R0) is equivalent to (Rx+R0)
// In case of base+displacement mode instructions if
// the offset is 0, usage of (Rx) is equivalent to 0(Rx)
TEXT asmtest(SB),DUPOK|NOSPLIT,$0
	// move constants
	MOVD $1, R3                     // 38600001

// license that can be found in the LICENSE file.

// This input was created by taking the instruction productions in
// the old assembler's (7a's) grammar and hand-writing complete
// instructions for each rule, to guarantee we cover the same space.

#include "../../../../../runtime/textflag.h"

TEXT	foo(SB), DUPOK|NOSPLIT, $-8

// arithmetic operations
	ADDW	$1, R2, R3
	ADDW	R1, R2, R3

// license that can be found in the LICENSE file.

// This input was created by taking the instruction productions in
// the old assembler's (5a's) grammar and hand-writing complete
// instructions for each rule, to guarantee we cover the same space.

#include "../../../../../runtime/textflag.h"

TEXT	foo(SB), DUPOK|NOSPLIT, $0

// ADD
//
//	LTYPE1 cond imsr ',' spreg ',' reg
//	{

	MOVW	R1, M1

	//	LMOVW mreg ',' rreg
	//	{
	//		outcode(int($1), &$2, 0, &$4);
	//	}
	MOVW	M1, R1
	MOVW	M1, R1


	//
	// integer operations
	// logical instructions
	// shift instructions
	// unary instructions
	//
	//	LADDW rreg ',' sreg ',' rreg
	//	{
	//		outcode(int($1), &$2, int($4), &$6);
	//	}
	ADD	R1, R2, R3

	//	LADDW imm ',' sreg ',' rreg
	//	{

two:
	RET
TEXT ·a12(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	JMP one
two:
	ORQ R15, R15
	RET
one:
	MOVL $0, R15
	JMP two

// Ensure 3-arg instructions get GOT-rewritten without errors.
// See issue 58735.
TEXT ·a13(SB), 0, $0-0
	MULXQ runtime·writeBarrier(SB), AX, CX
	RET

// Various special cases in the use-R15-after-global-access-when-dynlinking check.

	SW	X5, 4(X6)				// 23225300
	SH	X5, (X6)				// 23105300
	SH	X5, 4(X6)				// 23125300
	SB	X5, (X6)				// 23005300
	SB	X5, 4(X6)				// 23025300

	// 2.7: Memory Ordering Instructions
	FENCE						// 0f00f00f

	// 5.2: Integer Computational Instructions (RV64I)
	ADDIW	$1, X5, X6				// 1b831200
	SLLIW	$1, X5, X6				// 1b931200
	SRLIW	$1, X5, X6				// 1bd31200
	SRAIW	$1, X5, X6				// 1bd31240
	ADDW	X5, X6, X7				// bb035300

// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

#include "../../../../../runtime/textflag.h"

TEXT asmtest(SB),DUPOK|NOSPLIT,$0
	// Instructions that were encoded with BYTE sequences.
	// Included to simplify validation of CL that fixed that.
	MOVQ (AX), M0  // 0f6f00
	MOVQ M0, 8(SP) // 0f7f442408
	MOVQ 8(SP), M0 // 0f6f442408
	MOVQ M0, (AX)  // 0f7f00