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src/cmd/asm/internal/asm/testdata/riscv64.s
SW X5, 4(X6) // 23225300 SH X5, (X6) // 23105300 SH X5, 4(X6) // 23125300 SB X5, (X6) // 23005300 SB X5, 4(X6) // 23025300 // 2.7: Memory Ordering Instructions FENCE // 0f00f00f // 5.2: Integer Computational Instructions (RV64I) ADDIW $1, X5, X6 // 1b831200 SLLIW $1, X5, X6 // 1b931200 SRLIW $1, X5, X6 // 1bd31200 SRAIW $1, X5, X6 // 1bd31240 ADDW X5, X6, X7 // bb035300
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Mar 22 04:42:21 GMT 2024 - 16.7K bytes - Viewed (0) -
.github/ISSUE_TEMPLATE/10_contributor_bug_report.yml
name: Bug Report description: Create a report to help us improve labels: [ "a:bug", "to-triage" ] assignees: [ ] body: - type: markdown attributes: value: | Please follow the instructions below. We receive dozens of issues every week, so to stay productive, we will close issues that don't provide enough information.
Others - Registered: Wed May 01 11:36:15 GMT 2024 - Last Modified: Fri Feb 16 07:49:32 GMT 2024 - 3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
MOVW R1, M1 // LMOVW mreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW M1, R1 MOVW M1, R1 // // integer operations // logical instructions // shift instructions // unary instructions // // LADDW rreg ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } ADD R1, R2, R3 // LADDW imm ',' sreg ',' rreg // {
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 6.7K bytes - Viewed (0) -
.github/ISSUE_TEMPLATE/20_contributor_feature_request.yml
name: Feature request description: Suggest an idea for this project labels: [ "a:feature", "to-triage" ] assignees: [ ] body: - type: markdown attributes: value: | Please follow the instructions below. We receive dozens of issues every week, so to stay productive, we will close issues that don't provide enough information.
Others - Registered: Wed May 01 11:36:15 GMT 2024 - Last Modified: Thu Apr 06 11:10:39 GMT 2023 - 1.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/386enc.s
// Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. #include "../../../../../runtime/textflag.h" TEXT asmtest(SB),DUPOK|NOSPLIT,$0 // Instructions that were encoded with BYTE sequences. // Included to simplify validation of CL that fixed that. MOVQ (AX), M0 // 0f6f00 MOVQ M0, 8(SP) // 0f7f442408 MOVQ 8(SP), M0 // 0f6f442408 MOVQ M0, (AX) // 0f7f00
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Apr 11 18:32:50 GMT 2023 - 1.2K bytes - Viewed (0) -
.github/ISSUE_TEMPLATE/03-gopls.yml
validations: required: false - type: textarea id: logs attributes: label: "Logs" description: "If possible please include gopls logs. Instructions for capturing them can be found here: https://github.com/golang/tools/blob/master/gopls/doc/troubleshooting.md#capture-logs" validations:
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Thu Jan 04 23:31:17 GMT 2024 - 1.8K bytes - Viewed (0) -
.github/ISSUE_TEMPLATE/30_contributor_regression.yml
You can use [the template](https://github.com/gradle/gradle-issue-reproducer) with a Gradle GitHub action set up to showcase your problem. In the rare cases where this is infeasible, we will also accept a detailed set of instructions. You can also use [Gradle Project Replicator](https://github.com/android/project-replicator) to reproduce the structure of your project. validations: required: true - type: input id: gradle-version
Others - Registered: Wed May 01 11:36:15 GMT 2024 - Last Modified: Fri Feb 16 07:49:32 GMT 2024 - 2.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/386.s
// This input was created by taking the instruction productions in // the old assembler's (8a's) grammar and hand-writing complete // instructions for each rule, to guarantee we cover the same space. #include "../../../../../runtime/textflag.h" TEXT foo(SB), DUPOK|NOSPLIT, $0 // LTYPE1 nonrem { outcode(int($1), &$2); } SETCC AX SETCC foo+4(SB) // LTYPE2 rimnon { outcode(int($1), &$2); } DIVB AX DIVB foo+4(SB) PUSHL $foo+4(SB)
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Apr 09 18:57:21 GMT 2019 - 2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc2.s
XOR $65536, R4 // 1e02001484f81500 XOR $4096, R4 // 3e00001484f81500 XOR $-1, R4, R5 // 1efcbf0285f81500 XOR $-1, R4 // 1efcbf0284f81500 MOVH R4, R5 // 85c04000a5c04800 // relocation instructions MOVW R4, name(SB) // 1e00001ac4038029 MOVWU R4, name(SB) // 1e00001ac4038029 MOVV R4, name(SB) // 1e00001ac403c029 MOVB R4, name(SB) // 1e00001ac4030029 MOVBU R4, name(SB) // 1e00001ac4030029
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Mon Apr 10 15:50:11 GMT 2023 - 3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64dynlinkerror.s
two: RET TEXT ·a12(SB), 0, $0-0 CMPL runtime·writeBarrier(SB), $0 JMP one two: ORQ R15, R15 RET one: MOVL $0, R15 JMP two // Ensure 3-arg instructions get GOT-rewritten without errors. // See issue 58735. TEXT ·a13(SB), 0, $0-0 MULXQ runtime·writeBarrier(SB), AX, CX RET // Various special cases in the use-R15-after-global-access-when-dynlinking check.
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Mar 15 20:45:41 GMT 2023 - 4.8K bytes - Viewed (0)