buildcfg.GOAMD64 >= 3 => (SARX(Q|L) x y)
L7:(SHL(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHLX(Q|L) x y)
L8:(SHR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHRX(Q|L) x y)
L9:
L10:// See comments in ARM64latelower.rules for why these are here.
L11:(MOVLQZX x) && zeroUpper32Bits(x,3) => x
L12:(MOVWQZX x) && zeroUpper48Bits(x,3) => x
L13:(MOVBQZX x) && zeroUpper56Bits(x,3) => x
...

		x := v_0
		if !(zeroUpper56Bits(x, 3)) {
			break
		}
		v.copyOf(x)
		return true
	}
	return false
}
func rewriteValueAMD64latelower_OpAMD64MOVLQZX(v *Value) bool {
	v_0 := v.Args[0]
	// match: (MOVLQZX x)
	// cond: zeroUpper32Bits(x,3)
	// result: x
	for {
		x := v_0
		if !(zeroUpper32Bits(x, 3)) {
			break
		}
		v.copyOf(x)
		return true
	}
	return false
}

(MOVLQSX (MOVBQSX x)) => (MOVBQSX x)
(MOVWQSX (MOVWQSX x)) => (MOVWQSX x)
(MOVWQSX (MOVBQSX x)) => (MOVBQSX x)
(MOVBQSX (MOVBQSX x)) => (MOVBQSX x)
(MOVLQZX (MOVLQZX x)) => (MOVLQZX x)
(MOVLQZX (MOVWQZX x)) => (MOVWQZX x)
(MOVLQZX (MOVBQZX x)) => (MOVBQZX x)
(MOVWQZX (MOVWQZX x)) => (MOVWQZX x)
(MOVWQZX (MOVBQZX x)) => (MOVBQZX x)
(MOVBQZX (MOVBQZX x)) => (MOVBQZX x)

	"MOVBLZX",
	"MOVBQSX",
	"MOVBQZX",
	"MOVBWSX",
	"MOVBWZX",
	"MOVDDUP",
	"MOVHLPS",
	"MOVHPD",
	"MOVHPS",
	"MOVL",
	"MOVLHPS",
	"MOVLPD",
	"MOVLPS",
	"MOVLQSX",
	"MOVLQZX",
	"MOVMSKPD",
	"MOVMSKPS",
	"MOVNTDQA",
	"MOVNTIL",
	"MOVNTIQ",
	"MOVNTO",
	"MOVNTPD",
	"MOVNTPS",
	"MOVNTQ",
	"MOVO",
	"MOVOU",
	"MOVQ",
	"MOVQL",
	"MOVQOZX",
	"MOVSB",

	PCDATA  $PCDATA_StackMapIndex, $0;	\
	MOVQ	(DX), R12;			\
	CALL	R12;				\
	/* copy register return values back */		\
	MOVQ    regArgs+40(FP), R12;		\
	CALL    ·spillArgs(SB);		\
	MOVLQZX	stackArgsSize+24(FP), CX;		\
	MOVLQZX	stackRetOffset+28(FP), BX;		\
	MOVQ	stackArgs+16(FP), DI;		\
	MOVQ	stackArgsType+0(FP), DX;		\
	MOVQ	SP, SI;				\
	ADDQ	BX, DI;				\
	ADDQ	BX, SI;				\
	SUBQ	BX, CX;				\
	CALL	callRet<>(SB);			\

		return true
	}
	// match: (MOVLQZX (ANDLconst [c] x))
	// result: (ANDLconst [c] x)
	for {
		if v_0.Op != OpAMD64ANDLconst {
			break
		}
		c := auxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		v.reset(OpAMD64ANDLconst)
		v.AuxInt = int32ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	// match: (MOVLQZX (MOVLQZX x))
	// result: (MOVLQZX x)
	for {

		{name: "MOVWQZX", argLength: 1, reg: gp11, asm: "MOVWLZX"}, // zero extend arg0 from int16 to int64
		{name: "MOVLQSX", argLength: 1, reg: gp11, asm: "MOVLQSX"}, // sign extend arg0 from int32 to int64
		{name: "MOVLQZX", argLength: 1, reg: gp11, asm: "MOVL"},    // zero extend arg0 from int32 to int64

		{name: "MOVLconst", reg: gp01, asm: "MOVL", typ: "UInt32", aux: "Int32", rematerializeable: true}, // 32 low bits of auxint

			},
			outputs: []outputInfo{
				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "MOVLQZX",
		argLen: 1,
		asm:    x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{