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Results 1 - 10 of 10 for MINSD (0.12 sec)
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src/math/hypot_amd64.s
JLE isInfOrNaN CMPQ AX, CX JLE isInfOrNaN // hypot = max * sqrt(1 + (min/max)**2) MOVQ BX, X0 MOVQ CX, X1 ORQ CX, BX JEQ isZero MOVAPD X0, X2 MAXSD X1, X0 MINSD X2, X1 DIVSD X0, X1 MULSD X1, X1 ADDSD $1.0, X1 SQRTSD X1, X1 MULSD X1, X0 MOVSD X0, ret+16(FP) RET isInfOrNaN: CMPQ AX, BX JEQ isInf CMPQ AX, CX JEQ isInf
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 15 15:48:19 UTC 2021 - 1.1K bytes - Viewed (0) -
test/codegen/floats.go
// Float Min/Max // // ---------------- // func Float64Min(a, b float64) float64 { // amd64:"MINSD" // arm64:"FMIND" // riscv64:"FMIN" // ppc64/power9:"XSMINJDP" // ppc64/power10:"XSMINJDP" return min(a, b) } func Float64Max(a, b float64) float64 { // amd64:"MINSD" // arm64:"FMAXD" // riscv64:"FMAX" // ppc64/power9:"XSMAXJDP" // ppc64/power10:"XSMAXJDP" return max(a, b)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 04 15:24:29 UTC 2024 - 4.9K bytes - Viewed (0) -
src/math/dim_amd64.s
JLT isMinNaN MOVQ R9, CX ANDQ DX, CX // y = |y| CMPQ AX, CX JLT isMinNaN // ±0 special cases ORQ CX, BX JEQ isMinZero MOVQ R8, X0 MOVQ R9, X1 MINSD X1, X0 MOVSD X0, ret+16(FP) RET isMinNaN: // return NaN MOVQ $NaN, AX isNegInf: // return -Inf MOVQ AX, ret+16(FP) RET isMinZero: MOVQ $(1<<63), AX // -0.0 CMPQ AX, R8 JEQ +3(PC)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 15 15:48:19 UTC 2021 - 1.9K bytes - Viewed (0) -
src/cmd/internal/obj/x86/anames.go
"LSSQ", "LSSW", "LTR", "LZCNTL", "LZCNTQ", "LZCNTW", "MASKMOVOU", "MASKMOVQ", "MAXPD", "MAXPS", "MAXSD", "MAXSS", "MFENCE", "MINPD", "MINPS", "MINSD", "MINSS", "MONITOR", "MOVAPD", "MOVAPS", "MOVB", "MOVBEL", "MOVBEQ", "MOVBEW", "MOVBLSX", "MOVBLZX", "MOVBQSX", "MOVBQZX", "MOVBWSX", "MOVBWZX", "MOVDDUP",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 11 18:32:50 UTC 2023 - 19.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc.s
MINPS X11, X11 // 450f5ddb MINSD (BX), X2 // f20f5d13 MINSD (R11), X2 // f2410f5d13 MINSD X2, X2 // f20f5dd2 MINSD X11, X2 // f2410f5dd3 MINSD (BX), X11 // f2440f5d1b MINSD (R11), X11 // f2450f5d1b MINSD X2, X11 // f2440f5dda
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Oct 08 21:38:44 UTC 2021 - 581.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
// builtin min. In particular, these aren't commutative, because on various // special cases the 2nd argument is preferred. {name: "MINSD", argLength: 2, reg: fp21, resultInArg0: true, asm: "MINSD"}, // min(arg0,arg1) {name: "MINSS", argLength: 2, reg: fp21, resultInArg0: true, asm: "MINSS"}, // min(arg0,arg1)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 98K bytes - Viewed (1) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
// (although that comment isn't exactly right, as the value overwritten is not simulated correctly). // t1 = MINSD x, y => incorrect if x==NaN or x==-0,y==+0 // t2 = MINSD t1, x => fixes x==NaN case // res = POR t1, t2 => fixes x==-0,y==+0 case // Note that this trick depends on the special property that (NaN OR x) produces a NaN (although
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/x86/x86asm/tables.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 16 22:24:28 UTC 2022 - 266.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteAMD64.go
return true } } func rewriteValueAMD64_OpMin64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Min64F <t> x y) // result: (POR (MINSD <t> (MINSD <t> x y) x) (MINSD <t> x y)) for { t := v.Type x := v_0 y := v_1 v.reset(OpAMD64POR) v0 := b.NewValue0(v.Pos, OpAMD64MINSD, t) v1 := b.NewValue0(v.Pos, OpAMD64MINSD, t)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 712.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MINSD", argLen: 2, resultInArg0: true, asm: x86.AMINSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)