// MOVQ and EMMS were introduced on the Pentium MMX.
	MOVQ	val+4(FP), M0
	MOVQ	M0, (AX)
	EMMS
	// This is essentially a no-op, but it provides required memory fencing.
	// It can be replaced with MFENCE, but MFENCE was introduced only on the Pentium4 (SSE2).
	XORL	AX, AX
	LOCK
	XADDL	AX, (SP)
	RET

// void	·Or8(byte volatile*, byte);
TEXT ·Or8(SB), NOSPLIT, $0-5
	MOVL	ptr+0(FP), AX
	MOVB	val+4(FP), BX

	VMOVNTDQ	Y0, 64(DI)
	VMOVNTDQ	Y0, 96(DI)
	SUBQ	$128, BX
	ADDQ	$128, DI
	CMPQ	BX, $128
	JAE	loop_avx2_huge
	// In the description of MOVNTDQ in [1]
	// "... fencing operation implemented with the SFENCE or MFENCE instruction
	// should be used in conjunction with MOVNTDQ instructions..."
	// [1] 64-ia-32-architectures-software-developer-manual-325462.pdf
	SFENCE
	VMOVDQU  Y0, -32(DI)(BX*1)
	VMOVDQU  Y0, -64(DI)(BX*1)

done:
	MOVL	AX, ret_lo+0(FP)
	MOVL	DX, ret_hi+4(FP)
	RET
fences:
	// MFENCE is instruction stream serializing and flushes the
	// store buffers on AMD. The serialization semantics of LFENCE on AMD
	// are dependent on MSR C001_1029 and CPU generation.
	// LFENCE on Intel does wait for all previous instructions to have executed.
	// Intel recommends MFENCE;LFENCE in its manuals before RDTSC to have all

//
// These four modes correspond to other well-known memory models on other CPUs.
// On ARM, aq corresponds to a dmb ishst, aq+rl corresponds to a dmb ish. On
// Intel, aq corresponds to an lfence, rl to an sfence, and aq+rl to an mfence
// (or a lock prefix).
//
// Go's memory model requires that
//   - if a read happens after a write, the read must observe the write, and
//     that

	"LSLL",
	"LSLQ",
	"LSLW",
	"LSSL",
	"LSSQ",
	"LSSW",
	"LTR",
	"LZCNTL",
	"LZCNTQ",
	"LZCNTW",
	"MASKMOVOU",
	"MASKMOVQ",
	"MAXPD",
	"MAXPS",
	"MAXSD",
	"MAXSS",
	"MFENCE",
	"MINPD",
	"MINPS",
	"MINSD",
	"MINSS",
	"MONITOR",
	"MOVAPD",
	"MOVAPS",
	"MOVB",
	"MOVBEL",
	"MOVBEQ",
	"MOVBEW",
	"MOVBLSX",
	"MOVBLZX",
	"MOVBQSX",
	"MOVBQZX",

	SHLQ	$32, DX
	ADDQ	DX, AX
	MOVQ	AX, ret+0(FP)
	RET
fences:
	// MFENCE is instruction stream serializing and flushes the
	// store buffers on AMD. The serialization semantics of LFENCE on AMD
	// are dependent on MSR C001_1029 and CPU generation.
	// LFENCE on Intel does wait for all previous instructions to have executed.
	// Intel recommends MFENCE;LFENCE in its manuals before RDTSC to have all

	MASKMOVDQU:      "MASKMOVDQU",
	MASKMOVQ:        "MASKMOVQ",
	MAXPD:           "MAXPD",
	MAXPS:           "MAXPS",
	MAXSD:           "MAXSD",
	MAXSS:           "MAXSS",
	MFENCE:          "MFENCE",
	MINPD:           "MINPD",
	MINPS:           "MINPS",
	MINSD:           "MINSD",
	MINSS:           "MINSS",
	MONITOR:         "MONITOR",
	MOV:             "MOV",
	MOVAPD:          "MOVAPD",

	MAXSS (BX), X11                         // f3440f5f1b
	MAXSS (R11), X11                        // f3450f5f1b
	MAXSS X2, X11                           // f3440f5fda
	MAXSS X11, X11                          // f3450f5fdb
	MFENCE                                  // 0faef0
	MINPD (BX), X2                          // 660f5d13
	MINPD (R11), X2                         // 66410f5d13
	MINPD X2, X2                            // 660f5dd2