// Zevex_r_v_k_rm.
	VMOVSD X2, X9, K5, X21 // 62b1b70d11d5 or 62e1b70d10ea
	VMOVSD X21, X2, K5, X9 // 62c1ef0d11e9 or 6231ef0d10cd
	VMOVSD X9, X21, K5, X2 // 6271d70511ca or 62d1d70510d1
	// Zevex_r_v_rm.
	VMOVSD X2, X9, X21 // 62b1b70811d5 or 62e1b70810ea
	VMOVSD X21, X2, X9 // 62c1ef0811e9 or 6231ef0810cd
	VMOVSD X9, X21, X2 // 6271d70011ca or 62d1d70010d1
	VPMOVDB X2, X21    // 62b27e0831d5

    // Test all escapes
    assertEquals(
        "a&quot;b&lt;c&gt;d&amp;e&quot;f&apos;", xmlAttributeEscaper.escape("a\"b<c>d&e\"f'"));
    // Test '\t', '\n' and '\r' are escaped.
    assertEquals("a&#x9;b&#xA;c&#xD;d", xmlAttributeEscaper.escape("a\tb\nc\rd"));
  }

  // Helper to assert common properties of xml escapers.
  static void assertBasicXmlEscaper(

	CANDI	$31, X10				// 7d89

	// 26.5.3: Compressed Integer Register-Register Operations
	CMV	X6, X5					// 9a82
	CADD	X9, X8					// 2694
	CAND	X9, X8					// 658c
	COR	X9, X8					// 458c
	CXOR	X9, X8					// 258c
	CSUB	X9, X8					// 058c
	CADDW	X9, X8					// 259c
	CSUBW	X9, X8					// 059c

	// 26.5.5: Compressed NOP Instruction
	CNOP						// 0100

	// 26.5.6: Compressed Breakpoint Instruction

:= arg1[5] x6 := arg1[6] x7 := arg1[7] x8 := arg1[8] x9 := arg1[0] var x10 uint64 var x11 uint64 x11, x10 = bits.Mul64(x9, arg2[8]) var x12 uint64 var x13 uint64 x13, x12 = bits.Mul64(x9, arg2[7]) var x14 uint64 var x15 uint64 x15, x14 = bits.Mul64(x9, arg2[6]) var x16 uint64 var x17 uint64 x17, x16 = bits.Mul64(x9, arg2[5]) var x18 uint64 var x19 uint64 x19, x18 = bits.Mul64(x9, arg2[4]) var x20 uint64 var x21 uint64 x21, x20 = bits.Mul64(x9, arg2[3]) var x22 uint64 var x23 uint64 x23, x22 = bits.Mul64(x9,...

  }

  private enum SmallEnum {
    X0,
    X1,
    X2
  }

  private enum MediumEnum {
    X0,
    X1,
    X2,
    X3,
    X4,
    X5,
    X6,
    X7,
    X8,
    X9,
    X10,
    X11,
    X12,
    X13,
    X14,
    X15,
    X16,
    X17,
    X18,
    X19,
    X20,
    X21,
    X22,
    X23,
    X24,
    X25,
    X26,

	VMOVQ		R4, V3.B[1]     // 8384eb72
	VMOVQ		R5, V4.B[3]     // a48ceb72
	VMOVQ		R6, V5.H[2]     // c5c8eb72
	VMOVQ		R7, V6.W[2]     // e6e8eb72
	VMOVQ		R8, V7.V[1]     // 07f5eb72
	XVMOVQ		R7, X9.W[2]     // e9c8eb76
	XVMOVQ		R8, X10.V[2]    // 0ae9eb76

	// Duplicate general-purpose register to vector
	VMOVQ		R4, V2.B16      // 82009f72
	VMOVQ		R5, V3.H8       // a3049f72
	VMOVQ		R6, V4.W4       // c4089f72