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Results 1 - 10 of 19 for FSQRTS (0.29 sec)
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test/codegen/math.go
} func sqrt32(x float32) float32 { // amd64:"SQRTSS" // 386/sse2:"SQRTSS" 386/softfloat:-"SQRTS" // arm64:"FSQRTS" // arm/7:"SQRTF" // mips/hardfloat:"SQRTF" mips/softfloat:-"SQRTF" // mips64/hardfloat:"SQRTF" mips64/softfloat:-"SQRTF" // wasm:"F32Sqrt" // ppc64x:"FSQRTS" // riscv64: "FSQRTS" return float32(math.Sqrt(float64(x))) } // Check that it's using integer registers func abs(x, y float64) {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 04 15:24:29 UTC 2024 - 6.2K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/anames.go
"FRCSR", "FSCSR", "FRRM", "FSRM", "FRFLAGS", "FSFLAGS", "FSRMI", "FSFLAGSI", "FLW", "FSW", "FADDS", "FSUBS", "FMULS", "FDIVS", "FMINS", "FMAXS", "FSQRTS", "FMADDS", "FMSUBS", "FNMADDS", "FNMSUBS", "FCVTWS", "FCVTLS", "FCVTSW", "FCVTSL", "FCVTWUS", "FCVTLUS", "FCVTSWU", "FCVTSLU", "FSGNJS", "FSGNJNS",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 18 01:40:37 UTC 2023 - 5.4K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/anames.go
"FRESCC", "FRIM", "FRIMCC", "FRIP", "FRIPCC", "FRIZ", "FRIZCC", "FRIN", "FRINCC", "FRSQRTE", "FRSQRTECC", "FSEL", "FSELCC", "FSQRT", "FSQRTCC", "FSQRTS", "FSQRTSCC", "CNTLZD", "CNTLZDCC", "CMPW", "CMPWU", "CMPB", "FTDIV", "FTSQRT", "DIVD", "DIVDCC", "DIVDE", "DIVDECC", "DIVDEU", "DIVDEUCC", "DIVDVCC",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/anames.go
"FMADDS", "FMOVD", "FMOVS", "FMSUB", "FMSUBS", "FMUL", "FMULS", "FNABS", "FNEG", "FNEGS", "LEDBR", "LDEBR", "LPDFR", "LNDFR", "FSUB", "FSUBS", "FSQRT", "FSQRTS", "FIEBR", "FIDBR", "CPSDR", "LTEBR", "LTDBR", "TCEB", "TCDB", "LDGR", "LGDR", "CEFBRA", "CDFBRA", "CEGBRA", "CDGBRA", "CFEBRA", "CFDBRA", "CGEBRA",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 7.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 30.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
FADDS F1, F0, F2 // 53011000 FSUBS F1, F0, F2 // 53011008 FMULS F1, F0, F2 // 53011010 FDIVS F1, F0, F2 // 53011018 FMINS F1, F0, F2 // 53011028 FMAXS F1, F0, F2 // 53111028 FSQRTS F0, F1 // d3000058 // 11.7: Single-Precision Floating-Point Conversion and Move Instructions FCVTWS F0, X5 // d31200c0 FCVTWS.RNE F0, X5 // d30200c0 FCVTWS.RTZ F0, X5 // d31200c0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
FMULS F4, F11 // b31700b4 FMUL F5, F10 // b31c00a5 FDIVS F6, F9 // b30d0096 FDIV F7, F8 // b31d0087 FABS F1, F2 // b3100021 FSQRTS F3, F4 // b3140043 FSQRT F5, F15 // b31500f5 FIEBR $0, F0, F1 // b3570010 FIDBR $7, F2, F3 // b35f7032 FMADD F1, F1, F1 // b31e1011
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 22 03:55:32 UTC 2023 - 21.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390XOps.go
{name: "NOTW", argLength: 1, reg: gp11, resultInArg0: true, clobberFlags: true}, // ^arg0 {name: "FSQRT", argLength: 1, reg: fp11, asm: "FSQRT"}, // sqrt(arg0) {name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS"}, // sqrt(arg0), float32 // Conditional register-register moves. // The aux for these values is an s390x.CCMask value representing the condition code mask.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 52.5K bytes - Viewed (0)