{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{1, 0},
				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:   "ADCzerocarry",

	AND $-9223372036854775808, R1, R1          // 21004192
	ANDW $4026540031, R29, R2                  // a2430412
	AND $34903429696192636, R12, R19           // 93910e92
	ANDW R9@>7, R19, R26                       // 7a1ec90a
	AND R9@>7, R19, R26                        // 7a1ec98a
	TSTW $2863311530, R24                      // 1ff30172
	TST R2, R0                                 // 1f0002ea
	TST $7, R2                                 // 5f0840f2

	print("r21  ", hex(c.r21()), "\n")
	print("r22  ", hex(c.r22()), "\t")
	print("r23  ", hex(c.r23()), "\n")
	print("r24  ", hex(c.r24()), "\t")
	print("r25  ", hex(c.r25()), "\n")
	print("r26  ", hex(c.r26()), "\t")
	print("r27  ", hex(c.r27()), "\n")
	print("r28  ", hex(c.r28()), "\t")
	print("r29  ", hex(c.r29()), "\n")
	print("r30  ", hex(c.r30()), "\t")
	print("r31  ", hex(c.r31()), "\n")

 */
.globl crosscall1
crosscall1:
	addi.d	$r3, $r3, -160
	st.d	$r1, $r3, 0
	st.d	$r23, $r3, 8
	st.d	$r24, $r3, 16
	st.d	$r25, $r3, 24
	st.d	$r26, $r3, 32
	st.d	$r27, $r3, 40
	st.d	$r28, $r3, 48
	st.d	$r29, $r3, 56
	st.d	$r30, $r3, 64
	st.d	$r2, $r3, 72
	st.d	$r22, $r3, 80
	fst.d	$f24, $r3, 88
	fst.d	$f25, $r3, 96
	fst.d	$f26, $r3, 104

//
// Note: g is R22

#define SAVE_R22_TO_R31(offset)	\
	MOVV	g,   ((offset)+(0*8))(R3)	\
	MOVV	R23, ((offset)+(1*8))(R3)	\
	MOVV	R24, ((offset)+(2*8))(R3)	\
	MOVV	R25, ((offset)+(3*8))(R3)	\
	MOVV	R26, ((offset)+(4*8))(R3)	\
	MOVV	R27, ((offset)+(5*8))(R3)	\
	MOVV	R28, ((offset)+(6*8))(R3)	\
	MOVV	R29, ((offset)+(7*8))(R3)	\
	MOVV	R30, ((offset)+(8*8))(R3)	\
	MOVV	R31, ((offset)+(9*8))(R3)

	ADD	$-7193, R24	// 2318e3e7
	ADDV	$-7193, R24	// 6318e3e7

//	LSUBW rreg ',' sreg ',' rreg
//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	SUB	R6, R26, R27	// 0346d822
	SUBU	R6, R26, R27	// 0346d823
	SUBV	R16, R17, R26	// 0230d02e
	SUBVU	R16, R17, R26	// 0230d02f

//	LSUBW imm ',' sreg ',' rreg
//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	SUB	$-3126, R17, R22	// 22360c36

	MOVD	R16, 64(R1)
	MOVD	R17, 72(R1)
	MOVD	R18, 80(R1)
	MOVD	R19, 88(R1)
	MOVD	R20, 96(R1)
	MOVD	R21,104(R1)
	MOVD	R22, 112(R1)
	MOVD	R23, 120(R1)
	MOVD	R24, 128(R1)
	MOVD	R25, 136(R1)
	MOVD	R26, 144(R1)
	MOVD	R27, 152(R1)
	MOVD	R28, 160(R1)
	MOVD	R29, 168(R1)
	MOVD	g, 176(R1) // R30
	MOVD	R31, 184(R1)
	FMOVD	F14, 192(R1)
	FMOVD	F15, 200(R1)
	FMOVD	F16, 208(R1)
	FMOVD	F17, 216(R1)

	{"R16", "R16"},
	{"R17", "R17"},
	{"R18", "R18"},
	{"R19", "R19"},
	{"R2", "R2"},
	{"R20", "R20"},
	{"R21", "R21"},
	{"R22", "R22"},
	{"R23", "R23"},
	{"R24", "R24"},
	{"R25", "R25"},
	{"R26", "R26"},
	{"R27", "R27"},
	{"R28", "R28"},
	{"R29", "R29"},
	{"R3", "R3"},
	{"R31", "R31"},
	{"R4", "R4"},
	{"R5", "R5"},
	{"R6", "R6"},
	{"R7", "R7"},
	{"R8", "R8"},
	{"R9", "R9"},

	ADD	$1024,R10,R10	// &tab[5]
	SLD	$2,R24,R24	// crc>>16&0xFF*4
	MOVWZ	(R10)(R24),R26	// tab[5][crc>>16&0xFF]
	XOR	R21,R26,R21	// xor done R26
	RLDICL	$56,R7,$56,R25	// crc>>8
	ADD	$1024,R10,R10	// &tab[6]
	SLD	$2,R25,R25	// crc>>8&FF*2
	MOVBZ   R7,R26          // crc&0xFF
	MOVWZ	(R10)(R25),R27	// tab[6][crc>>8&0xFF]
	ADD 	$1024,R10,R10   // &tab[7]
	SLD	$2,R26,R26	// crc&0xFF*2
	XOR	R21,R27,R21	// xor done R27

Examples:

	ADD R19>>30, R10, R24     <=>    add x24, x10, x19, lsr #30
	ADDW R26->24, R21, R15    <=>    add w15, w21, w26, asr #24

Extended registers are written as <Rm>{.<extend>{<<<amount>}}.
<extend> can be UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW or SXTX.

Examples:

	ADDS R19.UXTB<<4, R9, R26     <=>    adds x26, x9, w19, uxtb #4
	ADDSW R14.SXTX, R14, R6       <=>    adds w6, w14, w14, sxtx