{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{1, 0},
				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:   "ADCzerocarry",

	AND $-9223372036854775808, R1, R1          // 21004192
	ANDW $4026540031, R29, R2                  // a2430412
	AND $34903429696192636, R12, R19           // 93910e92
	ANDW R9@>7, R19, R26                       // 7a1ec90a
	AND R9@>7, R19, R26                        // 7a1ec98a
	TSTW $2863311530, R24                      // 1ff30172
	TST R2, R0                                 // 1f0002ea
	TST $7, R2                                 // 5f0840f2

	ADD	$-7193, R24	// 2318e3e7
	ADDV	$-7193, R24	// 6318e3e7

//	LSUBW rreg ',' sreg ',' rreg
//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	SUB	R6, R26, R27	// 0346d822
	SUBU	R6, R26, R27	// 0346d823
	SUBV	R16, R17, R26	// 0230d02e
	SUBVU	R16, R17, R26	// 0230d02f

//	LSUBW imm ',' sreg ',' rreg
//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	SUB	$-3126, R17, R22	// 22360c36

	{"R16", "R16"},
	{"R17", "R17"},
	{"R18", "R18"},
	{"R19", "R19"},
	{"R2", "R2"},
	{"R20", "R20"},
	{"R21", "R21"},
	{"R22", "R22"},
	{"R23", "R23"},
	{"R24", "R24"},
	{"R25", "R25"},
	{"R26", "R26"},
	{"R27", "R27"},
	{"R28", "R28"},
	{"R29", "R29"},
	{"R3", "R3"},
	{"R31", "R31"},
	{"R4", "R4"},
	{"R5", "R5"},
	{"R6", "R6"},
	{"R7", "R7"},
	{"R8", "R8"},
	{"R9", "R9"},

	ADD	$1024,R10,R10	// &tab[5]
	SLD	$2,R24,R24	// crc>>16&0xFF*4
	MOVWZ	(R10)(R24),R26	// tab[5][crc>>16&0xFF]
	XOR	R21,R26,R21	// xor done R26
	RLDICL	$56,R7,$56,R25	// crc>>8
	ADD	$1024,R10,R10	// &tab[6]
	SLD	$2,R25,R25	// crc>>8&FF*2
	MOVBZ   R7,R26          // crc&0xFF
	MOVWZ	(R10)(R25),R27	// tab[6][crc>>8&0xFF]
	ADD 	$1024,R10,R10   // &tab[7]
	SLD	$2,R26,R26	// crc&0xFF*2
	XOR	R21,R27,R21	// xor done R27

Examples:

	ADD R19>>30, R10, R24     <=>    add x24, x10, x19, lsr #30
	ADDW R26->24, R21, R15    <=>    add w15, w21, w26, asr #24

Extended registers are written as <Rm>{.<extend>{<<<amount>}}.
<extend> can be UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW or SXTX.

Examples:

	ADDS R19.UXTB<<4, R9, R26     <=>    adds x26, x9, w19, uxtb #4
	ADDSW R14.SXTX, R14, R6       <=>    adds w6, w14, w14, sxtx

 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

package org.gradle.integtests.tooling.r26

import org.gradle.integtests.tooling.CancellationSpec
import org.gradle.integtests.tooling.fixture.TestResultHandler
import org.gradle.tooling.GradleConnector
import org.gradle.tooling.ProjectConnection

	print("r21  ", hex(c.r21()), "\n")
	print("r22  ", hex(c.r22()), "\t")
	print("r23  ", hex(c.r23()), "\n")
	print("r24  ", hex(c.r24()), "\t")
	print("r25  ", hex(c.r25()), "\n")
	print("r26  ", hex(c.r26()), "\t")
	print("r27  ", hex(c.r27()), "\n")
	print("r28  ", hex(c.r28()), "\t")
	print("r29  ", hex(c.r29()), "\n")
	print("r30  ", hex(c.r30()), "\t")
	print("r31  ", hex(c.r31()), "\n")

	// Using a tail call here cleans up tracebacks since we won't stop
	// at an intermediate systemstack.
	MOVD	0(R26), R3	// code pointer
	MOVD.P	16(RSP), R30	// restore LR
	SUB	$8, RSP, R29	// restore FP
	B	(R3)

// func switchToCrashStack0(fn func())
TEXT runtime·switchToCrashStack0<ABIInternal>(SB), NOSPLIT, $0-8
	MOVD	R0, R26    // context register
	MOVD	g_m(g), R1 // curm

	// set g to gcrash

	MSR	R2, CNTV_CTL_EL0                   // 22e31bd5
	MRS	CNTV_CVAL_EL0, R8                  // 48e33bd5
	MSR	R26, CNTV_CVAL_EL0                 // 5ae31bd5
	MRS	CNTV_TVAL_EL0, R6                  // 06e33bd5
	MSR	R19, CNTV_TVAL_EL0                 // 13e31bd5
	MRS	CNTKCTL_EL1, R16                   // 10e138d5
	MSR	R26, CNTKCTL_EL1                   // 1ae118d5
	MRS	CNTPCT_EL0, R9                     // 29e03bd5