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Results 1 - 3 of 3 for UXTX (0.02 sec)

  1. src/cmd/asm/internal/arch/arm64.go

    			// effective address of memory is a base register value and an offset register value.
    			if a.Type == obj.TYPE_MEM {
    				a.Index = arm64.REG_UXTW + Rnum
    			} else {
    				a.Reg = arm64.REG_UXTW + Rnum
    			}
    		case "UXTX":
    			if a.Type == obj.TYPE_MEM {
    				return errors.New("invalid shift for the register offset addressing mode")
    			}
    			a.Reg = arm64.REG_UXTX + Rnum
    		case "SXTB":
    			if a.Type == obj.TYPE_MEM {
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Feb 14 15:13:11 UTC 2025
    - 10.3K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/arm64.s

    	ADDW	R2.SXTW, R10, R12               // 4cc1220b
    	ADD	R19.UXTX, R14, R17              // d161338b
    	ADDSW	R19.UXTW, R14, R17              // d141332b
    	ADDS	R12.SXTX, R3, R1                // 61e02cab
    	SUB	R19.UXTH<<4, R2, R21            // 553033cb
    	SUBW	R1.UXTX<<1, R3, R2              // 6264214b
    	SUBS	R3.UXTX, R8, R9                 // 096123eb
    	SUBSW	R17.UXTH, R15, R21              // f521316b
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 95.3K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/arm64error.s

    	ADDSW	R7->32, R14, R13                                 // ERROR "shift amount out of range 0 to 31"
    	ADD	R1.UXTB<<5, R2, R3                               // ERROR "shift amount out of range 0 to 4"
    	ADDS	R1.UXTX<<7, R2, R3                               // ERROR "shift amount out of range 0 to 4"
    	ADDS	R5, R6, RSP                                      // ERROR "illegal destination register"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 37.9K bytes
    - Viewed (0)
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