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Results 1 - 4 of 4 for UXTW (0.02 sec)
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src/cmd/asm/internal/asm/testdata/arm64.s
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Mar 26 10:48:50 UTC 2025 - 95.3K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm64.go
} a.Reg = arm64.REG_UXTB + Rnum case "UXTH": if a.Type == obj.TYPE_MEM { return errors.New("invalid shift for the register offset addressing mode") } a.Reg = arm64.REG_UXTH + Rnum case "UXTW": // effective address of memory is a base register value and an offset register value. if a.Type == obj.TYPE_MEM { a.Index = arm64.REG_UXTW + Rnum } else { a.Reg = arm64.REG_UXTW + Rnum }
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Fri Feb 14 15:13:11 UTC 2025 - 10.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64error.s
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Mar 26 10:48:50 UTC 2025 - 37.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/parse.go
num := int16(0) isAmount := true // Amount is zero by default ext := "" if p.peek() == lex.LSH { // (Rn)(Rm<<2), the shifted offset register. ext = "LSL" } else { // (Rn)(Rm.UXTW<1), the extended offset register. // Rm.UXTW<<3, the extended register. p.get('.') tok := p.next() ext = tok.String() } if p.peek() == lex.LSH { // parses left shift amount applied after extension: <<Amount
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Fri Feb 14 15:13:11 UTC 2025 - 37.3K bytes - Viewed (0)