ADD $(2280<<12), R25, R11                  // ADD $9338880, R25, R11            // 2ba36391
	ADDW R13->5, R11, R7                       // 67158d0b
	ADD R25<<54, R17, R16                      // 30da198b
	ADDSW R12.SXTX<<1, R29, R7                 // a7e72c2b
	ADDS R24.UXTX<<4, R25, R21                 // 357338ab
	ADDSW $(3525<<12), R3, R11                 // ADDSW $14438400, R3, R11          // 6b147731

			}
			a.Reg = arm64.REG_SXTH + Rnum
		case "SXTW":
			if a.Type == obj.TYPE_MEM {
				a.Index = arm64.REG_SXTW + Rnum
			} else {
				a.Reg = arm64.REG_SXTW + Rnum
			}
		case "SXTX":
			if a.Type == obj.TYPE_MEM {
				a.Index = arm64.REG_SXTX + Rnum
			} else {
				a.Reg = arm64.REG_SXTX + Rnum
			}
		case "LSL":
			a.Index = arm64.REG_LSL + Rnum
		default:

	MOVD.P	300(R2), R3                                      // ERROR "offset out of range [-256,255]"
	MOVD.P	R3, 344(R2)                                      // ERROR "offset out of range [-256,255]"
	MOVD	(R3)(R7.SXTX<<2), R8                             // ERROR "invalid index shift amount"
	MOVWU	(R5)(R4.UXTW<<3), R10                            // ERROR "invalid index shift amount"

		return "", obj.ABI0, false
	}
	return name, abi, true
}

// registerIndirect parses the general form of a register indirection.
// It can be (R1), (R2*scale), (R1)(R2*scale), (R1)(R2.SXTX<<3) or (R1)(R2<<3)
// where R1 may be a simple register or register pair R:R or (R, R) or (R+R).
// Or it might be a pseudo-indirection like (FP).
// We are sitting on the opening parenthesis.

<code>R0.SXTB&lt;&lt;imm</code>: left shift the result of <code>R0.SXTB</code> by <code>imm</code> bits.
The <code>imm</code> value can be 0, 1, 2, 3, or 4.
The other extensions include <code>SXTH</code> (16-bit), <code>SXTW</code> (32-bit), and <code>SXTX</code> (64-bit).
</li>

<li>
<code>(R5, R6)</code>: Register pair for <code>LDAXP</code>/<code>LDP</code>/<code>LDXP</code>/<code>STLXP</code>/<code>STP</code>/<code>STP</code>.
</li>

</ul>

<p>