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Results 1 - 10 of 17 for RegAlloc (0.14 sec)
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src/cmd/compile/internal/ssa/compile.go
{"schedule", "late nilcheck"}, // flagalloc needs instructions to be scheduled. {"schedule", "flagalloc"}, // regalloc needs flags to be allocated first. {"flagalloc", "regalloc"}, // loopRotate will confuse regalloc. {"regalloc", "loop rotate"}, // trim needs regalloc to be done first. {"regalloc", "trim"}, // memcombine works better if fuse happens first, to help merge stores. {"late fuse", "memcombine"},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 22 14:55:18 UTC 2024 - 18.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/stackalloc.go
} } } func (f *Func) getHome(vid ID) Location { if int(vid) >= len(f.RegAlloc) { return nil } return f.RegAlloc[vid] } func (f *Func) setHome(v *Value, loc Location) { for v.ID >= ID(len(f.RegAlloc)) { f.RegAlloc = append(f.RegAlloc, nil) } f.RegAlloc[v.ID] = loc } func (s *stackAllocState) buildInterferenceGraph() { f := s.f
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Feb 29 21:29:41 UTC 2024 - 12.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/value.go
func (v *Value) Reg() int16 { reg := v.Block.Func.RegAlloc[v.ID] if reg == nil { v.Fatalf("nil register for value: %s\n%s\n", v.LongString(), v.Block.Func) } return reg.(*Register).objNum } // Reg0 returns the register assigned to the first output of v, in cmd/internal/obj/$ARCH numbering. func (v *Value) Reg0() int16 { reg := v.Block.Func.RegAlloc[v.ID].(LocPair)[0] if reg == nil {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 03 16:40:22 UTC 2024 - 16.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/check.go
if valueMark[v.ID] { f.Fatalf("used value v%d in free list", v.ID) } } // Check to make sure all args dominate uses. if f.RegAlloc == nil { // Note: regalloc introduces non-dominating args. // See TODO in regalloc.go. sdom := f.Sdom() for _, b := range f.Blocks { for _, v := range b.Values { for i, arg := range v.Args { x := arg.Block y := b
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 09 16:41:23 UTC 2024 - 17.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/schedule.go
// are not stomped (similar to the closure pointer above). // In particular, they need to come before regular OpArg operations because // of how regalloc places spill code (see regalloc.go:placeSpills:mustBeFirst). if b != f.Entry { f.Fatalf("%s appeared outside of entry block, b=%s", v.Op, b.String()) } score[v.ID] = ScorePhi
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 08 15:53:17 UTC 2024 - 16.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/likelyadjust.go
children []*loop // loops nested directly within this loop. Initialized by assembleChildren(). exits []*Block // exits records blocks reached by exits from this loop. Initialized by findExits(). // Next three fields used by regalloc and/or // aid in computation of inner-ness and list of blocks. nBlocks int32 // Number of blocks in this loop but not within inner loops
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Oct 31 21:41:20 UTC 2022 - 15.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go
"R11", "R12", "R13", "R14", "R15", "R16", "R17", "R18", "R19", "R20", "R21", "R22", // R23 = REGTMP not used in regalloc "R24", "R25", // R26 reserved by kernel // R27 reserved by kernel // R28 = REGSB not used in regalloc "SP", // aka R29 "g", // aka R30 "R31", // aka REGLINK "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", "F8",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 03:36:31 UTC 2023 - 25.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
// H (half word) = 16 bit // HU = 16 bit unsigned // B (byte) = 8 bit // BU = 8 bit unsigned // F (float) = 32 bit float // D (double) = 64 bit float // Note: registers not used in regalloc are not included in this list, // so that regmask stays within int64 // Be careful when hand coding regmasks. var regNamesLOONG64 = []string{ "R0", // constant 0 "R1", "SP", // aka R3 "R4", "R5", "R6",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:19 UTC 2023 - 25.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
// BC 16,0,loop branch ctr // For this purpose, VS32 and VS33 are treated as // scratch registers. Since regalloc does not // track vector registers, even if it could be marked // as clobbered it would have no effect. // TODO: If vector registers are managed by regalloc // mark these as clobbered. // // Bytes not moved by this loop are moved // with a combination of the following instructions,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssagen/pgen.go
// keep their relative offsets correct, treat them all as used. continue } if needAlloc(ln) { ln.SetUsed(false) } } for _, l := range f.RegAlloc { if ls, ok := l.(ssa.LocalSlot); ok { ls.N.SetUsed(true) } } for _, b := range f.Blocks { for _, v := range b.Values { if n, ok := v.Aux.(*ir.Name); ok { switch n.Class {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 13.1K bytes - Viewed (0)