SC	R1, (R2)	// e0410000

//	LMOVH rreg ',' addr
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	MOVH	R13, (R7)	// a4ed0000
	MOVH	R10, 61(R23)	// a6ea003d
	MOVH	R8, -33(R12)	// a588ffdf
	MOVHU	R13, (R7)	// a4ed0000
	MOVHU	R10, 61(R23)	// a6ea003d
	MOVHU	R8, -33(R12)	// a588ffdf

//	LMOVB rreg ',' addr
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	MOVB	R1, foo<>+3(SB)

	BIC R12@>13, R12, R19                      // 9335ec8a
	BICSW R25->20, R3, R20                     // 7450b96a
	BICS R19->12, R1, R23                      // 3730b3ea
	BICS R19, R1, R23                          // 370033ea
	BICS R19>>0, R1, R23                       // 370073ea
	CALL -1(PC)                                // ffffff97
	CALL (R15)                                 // e0013fd6

	{"R13", "R13"},
	{"R14", "R14"},
	{"R15", "R15"},
	{"R16", "R16"},
	{"R17", "R17"},
	{"R18", "R18"},
	{"R19", "R19"},
	{"R2", "R2"},
	{"R20", "R20"},
	{"R21", "R21"},
	{"R22", "R22"},
	{"R23", "R23"},
	{"R24", "R24"},
	{"R25", "R25"},
	{"R26", "R26"},
	{"R27", "R27"},
	{"R28", "R28"},
	{"R29", "R29"},
	{"R3", "R3"},
	{"R31", "R31"},
	{"R4", "R4"},
	{"R5", "R5"},
	{"R6", "R6"},

General purpose registers are named <code>R0</code> through <code>R31</code>,
floating point registers are <code>F0</code> through <code>F31</code>.
</p>

<p>
<code>R30</code> is reserved to point to <code>g</code>.
<code>R23</code> is used as a temporary register.
</p>

<p>
In a <code>TEXT</code> directive, the frame size <code>$-4</code> for MIPS or
<code>$-8</code> for MIPS64 instructs the linker not to save <code>LR</code>.
</p>