instructions["JZ"] = x86.AJEQ   /* alternate */
	instructions["MASKMOVDQU"] = x86.AMASKMOVOU
	instructions["MOVD"] = x86.AMOVQ
	instructions["MOVDQ2Q"] = x86.AMOVQ
	instructions["MOVNTDQ"] = x86.AMOVNTO
	instructions["MOVOA"] = x86.AMOVO
	instructions["PSLLDQ"] = x86.APSLLO
	instructions["PSRLDQ"] = x86.APSRLO
	instructions["PADDD"] = x86.APADDL
	// Spellings originally used in CL 97235.

	MOVV		(R14)(R13), R12	// cc350c38

	// STX.{B,H,W,D} instructions
	MOVB		R12, (R14)(R13)	// cc351038
	MOVH		R12, (R14)(R13)	// cc351438
	MOVW		R12, (R14)(R13)	// cc351838
	MOVV		R12, (R14)(R13)	// cc351c38

	// FLDX.{S,D} instructions
	MOVF		(R14)(R13), F2	// c2353038
	MOVD		(R14)(R13), F2	// c2353438

	// FSTX.{S,D} instructions
	MOVF		F2, (R14)(R13)	// c2353838
	MOVD		F2, (R14)(R13)	// c2353c38

Function is the outermost frame of the call stack. Traceback should stop at this function.
</li>
</ul>

<h3 id="special-instructions">Special instructions</h3>

<p>
The <code>PCALIGN</code> pseudo-instruction is used to indicate that the next instruction should be aligned
to a specified boundary by padding with no-op instructions.
</p>

<p>
It is currently supported on arm64, amd64, ppc64, loong64 and riscv64.

					p.errorf("invalid addressing modes for 1st or 3rd operand to %s instruction, must be register pair", op)
					return
				}
				// For ARM64 CASP-like instructions, its 2nd destination operand is register pair(Rt, Rt+1) that can
				// not fit into prog.RegTo2, so save it to the prog.RestArgs.
				prog.AddRestDest(a[2])
			case isARM64SVE(op):
				// SVE instructions, see arm64/goops_gen.go
				prog.From = a[0]

            <phase>process-classes</phase>
            <goals>
              <goal>manifest</goal>
            </goals>
          </execution>
        </executions>
        <configuration>
          <instructions>
            <!-- Silence a warning that claims that META-INF/versions/9/... is the "wrong directory" for our classes. -->
            <_fixupmessages>^Classes found in the wrong directory: .*</_fixupmessages>

//	LMOVW mreg ',' rreg
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	MOVW	M1, R1 // 40010800
	MOVV	M1, R1 // 40210800


//
// integer operations
// logical instructions
// shift instructions
// unary instructions
//
//	LADDW rreg ',' sreg ',' rreg
//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	ADD	R5, R9, R10	// 01255020
	ADDU	R13, R14, R19	// 01cd9821

			</plugin>
			<plugin>
				<groupId>org.apache.felix</groupId>
				<artifactId>maven-bundle-plugin</artifactId>
				<version>6.0.0</version>
				<extensions>true</extensions>

				<configuration>
					<instructions>
						<Bundle-Version>${osgi.version}</Bundle-Version>
						<Bundle-License>LGPL</Bundle-License>
						<Bundle-Vendor>CodeLibs</Bundle-Vendor>
						<Bundle-SymbolicName>org.codelibs.jcifs</Bundle-SymbolicName>

```
## Typhinweise und –annotationen { #type-hints-and-annotations }
```

- Do not modify the hyphens in the content in headers inside of curly braces, which you shall not translate.

### German instructions, when to use and when not to use hyphens in words (written in first person, which is you).

Here are the general instructions for the tasks you can perform.

Thanks a lot for your help. 🙇

## Be Nice

First of all, be nice. 😊

You probably are super nice if you were added to the team, but it's worth mentioning it. 🤓

### When Things are Difficult

When things are great, everything is easier, so that doesn't need much instructions. But when things are difficult, here are some guidelines.

* <abbr title="Input/Output: disk reading or writing, network communications.">I/O</abbr>.

////

//// tab | Info

"title" attributes of "abbr" elements are translated following some specific instructions.

Translations can add their own "abbr" elements which the LLM should not remove. E.g. to explain English words.

See section `### HTML abbr elements` in the general prompt in `scripts/translate.py`.

////