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Results 21 - 30 of 95 for vmov (0.17 sec)
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src/runtime/asm_arm64.s
CBZ R10, noaes MOVD $runtime·aeskeysched+0(SB), R3 VEOR V0.B16, V0.B16, V0.B16 VLD1 (R3), [V2.B16] VLD1 (R0), V0.S[1] VMOV R1, V0.S[0] AESE V2.B16, V0.B16 AESMC V0.B16, V0.B16 AESE V2.B16, V0.B16 AESMC V0.B16, V0.B16 AESE V2.B16, V0.B16 VMOV V0.D[0], R0 RET noaes: B runtime·memhash32Fallback<ABIInternal>(SB) // func memhash64(p unsafe.Pointer, h uintptr) uintptr
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 11 20:38:24 UTC 2024 - 43.4K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm/armasm/inst.go
// The Index field specifies the index number, // but the size of the fraction is not specified. // It must be inferred from the instruction and the register type. // For example, in a VMOV instruction, RegX{D5, 1} represents // the top 32 bits of the 64-bit D5 register. type RegX struct { Reg Reg Index int } func (RegX) IsArg() {} func (r RegX) String() string {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 29 22:23:32 UTC 2017 - 7.5K bytes - Viewed (0) -
src/cmd/internal/obj/arm/asm5.go
o1 |= (uint32(p.To.Reg) & 15) << 12 o1 |= ((uint32(p.Scond) & C_SCOND) ^ C_SCOND_XOR) << 28 case 80: /* fmov zfcon,freg */ if p.As == AMOVD { o1 = 0xeeb00b00 // VMOV imm 64 o2 = c.oprrr(p, ASUBD, int(p.Scond)) } else { o1 = 0x0eb00a00 // VMOV imm 32 o2 = c.oprrr(p, ASUBF, int(p.Scond)) } v := int32(0x70) // 1.0 r := (int(p.To.Reg) & 15) << 0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 79.4K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/asm7.go
{AVMOV, C_ELEM, C_NONE, C_NONE, C_ZREG, C_NONE, 73, 4, 0, 0, 0}, {AVMOV, C_ELEM, C_NONE, C_NONE, C_ELEM, C_NONE, 92, 4, 0, 0, 0}, {AVMOV, C_ELEM, C_NONE, C_NONE, C_VREG, C_NONE, 80, 4, 0, 0, 0}, {AVMOV, C_ZREG, C_NONE, C_NONE, C_ARNG, C_NONE, 82, 4, 0, 0, 0}, {AVMOV, C_ZREG, C_NONE, C_NONE, C_ELEM, C_NONE, 78, 4, 0, 0, 0}, {AVMOV, C_ARNG, C_NONE, C_NONE, C_ARNG, C_NONE, 83, 4, 0, 0, 0},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 201.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
VMOVW -104(R17), W24 // 7be68e22 VMOVD (R3), W2 // 780018a3 VMOVD 128(R23), W19 // 7810bce3 VMOVD -256(R31), W0 // 7be0f823 VMOVB W8, (R0) // 78000224 VMOVB W0, 511(R3) // 79ff1824 VMOVB W21, -512(R12) // 7a006564 VMOVH W12, (R24) // 7800c325 VMOVH W8, 110(R19) // 78379a25 VMOVH W3, -70(R12) // 7bdd60e5 VMOVW W31, (R3) // 78001fe6 VMOVW W16, 64(R20) // 7810a426
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/internal/obj/mips/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 1.4K bytes - Viewed (0) -
src/cmd/internal/obj/mips/asm0.go
case 34: /* mov $con,fr ==> or/add $i,t; mov t,fr */ a := AADDU if o.a1 == C_ANDCON { a = AOR } v := c.regoff(&p.From) o1 = OP_IRR(c.opirr(a), uint32(v), obj.REG_NONE, REGTMP) o2 = OP_RRR(SP(2, 1)|(4<<21), REGTMP, obj.REG_NONE, p.To.Reg) /* mtc1 */ case 35: /* mov r,lext/auto/oreg ==> sw o(REGTMP) */ r := p.To.Reg
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 17:46:09 UTC 2024 - 53.6K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/tables.go
{0xfffffc00, 0x9e660000, FMOV, instArgs{arg_Xd, arg_Dn}, nil}, // FMOV <Xd>, <Vn>.D[1] {0xfffffc00, 0x9eae0000, FMOV, instArgs{arg_Xd, arg_Vn_arrangement_D_index__1}, nil}, // FMOV <Sd>, <Sn> {0xfffffc00, 0x1e204000, FMOV, instArgs{arg_Sd, arg_Sn}, nil}, // FMOV <Dd>, <Dn> {0xfffffc00, 0x1e604000, FMOV, instArgs{arg_Dd, arg_Dn}, nil}, // FMOV <Sd>, #<imm>
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 16 17:57:48 UTC 2017 - 211.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(MOVHZreg y:(MOV(H|B)Zreg _)) => y // repeat (MOVHZreg y:(MOVHBRload _ _)) => y (MOVHreg y:(MOV(H|B)reg _)) => y // repeat (MOV(H|HZ)reg y:(MOV(HZ|H)reg x)) => (MOV(H|HZ)reg x) // W - there are more combinations than these (MOV(WZ|WZ|WZ|W|W|W)reg y:(MOV(WZ|HZ|BZ|W|H|B)reg _)) => y // repeat (MOVWZreg y:(MOV(H|W)BRload _ _)) => y (MOV(W|WZ)reg y:(MOV(WZ|W)reg x)) => (MOV(W|WZ)reg x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
for p := cursym.Func().Text; p != nil; p = p.Link { switch p.As { case obj.AGETCALLERPC: if cursym.Leaf() { // MOV LR, Rd p.As = AMOV p.From.Type = obj.TYPE_REG p.From.Reg = REG_LR } else { // MOV (RSP), Rd p.As = AMOV p.From.Type = obj.TYPE_MEM p.From.Reg = REG_SP } case obj.ACALL, obj.ADUFFZERO, obj.ADUFFCOPY: switch p.To.Type {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0)