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Results 11 - 20 of 28 for ANDCC (0.47 sec)
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src/crypto/subtle/xor_ppc64x.s
BLE CR6, small // <= 8 BLT CR7, xor32 // Case for 32 ≤ n < 64 bytes // Case for n ≥ 64 bytes preloop64: SRD $6, R6, R7 // Set up loop counter MOVD R7, CTR MOVD $16, R10 MOVD $32, R14 MOVD $48, R15 ANDCC $63, R6, R9 // Check for tailing bytes for later PCALIGN $16 // Case for >= 64 bytes // Process 64 bytes per iteration // Load 4 vectors of a and b // XOR the corresponding vectors
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 2.9K bytes - Viewed (0) -
test/codegen/bool.go
// ppc64x/power8:"FCMP","ISEL",-"SETBC\tCR0LT" b := !(x >= y) return b } func TestLogicalCompareZero(x *[64]uint64) { // ppc64x:"ANDCC",^"AND" b := x[0]&3 if b!=0 { x[0] = b } // ppc64x:"ANDCC",^"AND" b = x[1]&x[2] if b!=0 { x[1] = b } // ppc64x:"ANDNCC",^"ANDN" b = x[1]&^x[2] if b!=0 { x[1] = b } // ppc64x:"ORCC",^"OR"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 13 22:12:32 UTC 2023 - 6.7K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/anames.go
"ADDCV", "ADDCVCC", "ADDME", "ADDMECC", "ADDMEVCC", "ADDMEV", "ADDE", "ADDECC", "ADDEVCC", "ADDEV", "ADDZE", "ADDZECC", "ADDZEVCC", "ADDZEV", "ADDEX", "AND", "ANDCC", "ANDN", "ANDNCC", "ANDISCC", "BC", "BCL", "BEQ", "BGE", "BGT", "BLE", "BLT", "BNE", "BVC", "BVS", "BDNZ", "BDZ", "CMP", "CMPU", "CMPEQB", "CNTLZW",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
test/codegen/comparisons.go
} func CmpLogicalToZero(a, b, c uint32, d, e uint64) uint64 { // ppc64x:"ANDCC",-"CMPW" // wasm:"I64Eqz",-"I32Eqz",-"I64ExtendI32U",-"I32WrapI64" if a&63 == 0 { return 1 } // ppc64x:"ANDCC",-"CMP" // wasm:"I64Eqz",-"I32Eqz",-"I64ExtendI32U",-"I32WrapI64" if d&255 == 0 { return 1 } // ppc64x:"ANDCC",-"CMP" // wasm:"I64Eqz",-"I32Eqz",-"I64ExtendI32U",-"I32WrapI64" if d&e == 0 {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 19 16:31:02 UTC 2024 - 15.2K bytes - Viewed (0) -
test/codegen/arithmetic.go
// arm:"AND\t[$]63",-".*udiv",-"SRA" // arm64:"TST\t[$]63",-"UDIV",-"ASR",-"AND" // ppc64x:"ANDCC",-"RLDICL",-"SRAD",-"CMP" a := n1%64 == 0 // signed divisible // 386:"TESTL\t[$]63",-"DIVL",-"SHRL" // amd64:"TESTQ\t[$]63",-"DIVQ",-"SHRQ" // arm:"AND\t[$]63",-".*udiv",-"SRA" // arm64:"TST\t[$]63",-"UDIV",-"ASR",-"AND" // ppc64x:"ANDCC",-"RLDICL",-"SRAD",-"CMP" b := n2%64 != 0 // signed indivisible return a, b }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 15:28:00 UTC 2024 - 15.2K bytes - Viewed (0) -
src/hash/crc32/crc32_ppc64le.s
XOR R21,R27,R21 // xor done R27 ADD $8,R5 // p = p[8:] MOVWZ (R10)(R26),R28 // tab[7][crc&0xFF] XOR R21,R28,R21 // xor done R28 MOVWZ R21,R7 // crc for next round BDNZ loop ANDCC $7,R6,R8 // any leftover bytes BEQ done // none --> done MOVD R8,CTR // byte count PCALIGN $16 // align short loop short: MOVBZ 0(R5),R8 // get v XOR R8,R7,R8 // byte(crc)^v -> R8
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 06 12:09:50 UTC 2024 - 13.1K bytes - Viewed (0) -
src/internal/bytealg/index_ppc64x.s
SLD $3, R9 // Set up for VSLO MTVSRD R9, V9 // Set up for VSLO VSLDOI $8, V9, V9, V9 // Set up for VSLO VSLO ONES, V9, SEPMASK // Mask for separator len(sep) < 16 loadge16: ANDCC $15, R5, R9 // Find byte offset of sep ADD R9, R6, R10 // Add sep len CMP R10, $16 // Check if sep len+offset > 16 BGT sepcross16 // Sep crosses 16 byte boundary
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 16:47:45 UTC 2023 - 31.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
{name: "ANDNCC", argLength: 2, reg: gp21, asm: "ANDNCC", typ: "(Int64,Flags)"}, // arg0&^arg1 sets CC {name: "ANDCC", argLength: 2, reg: gp21, asm: "ANDCC", commutative: true, typ: "(Int64,Flags)"}, // arg0&arg1 sets CC {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true}, // arg0|arg1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
test/codegen/shift.go
// ppc64x: -"MOVWZ" y[0] = uint64((a >> 6) & 0x1c) // ppc64x: -"MOVWZ" y[1] = uint64(uint32(b)<<6) + 1 // ppc64x: -"MOVHZ", -"MOVWZ" y[2] = uint64((uint16(a) >> 9) & 0x1F) // ppc64x: -"MOVHZ", -"MOVWZ", -"ANDCC" y[3] = uint64(((uint16(a) & 0xFF0) >> 9) & 0x1F) } // 128 bit shifts func check128bitShifts(x, y uint64, bits uint) (uint64, uint64) { s := bits & 63 ŝ := (64 - bits) & 63
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 21 18:53:43 UTC 2024 - 12.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64latelower.go
break } z := v_0.Args[0] if z.Op != OpPPC64ADDCC { break } v.reset(OpSelect1) v.Type = t v.AddArg(z) return true } // match: (CMPconst <t> [0] (Select0 z:(ANDCC x y))) // result: (Select1 <t> z) for { t := v.Type if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpSelect0 { break } z := v_0.Args[0] if z.Op != OpPPC64ANDCC { break }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 16.5K bytes - Viewed (0)