\f38b"}.fa-cube:before{content:"\f1b2"}.fa-cubes:before{content:"\f1b3"}.fa-cut:before{content:"\f0c4"}.fa-cuttlefish:before{content:"\f38c"}.fa-d-and-d:before{content:"\f38d"}.fa-d-and-d-beyond:before{content:"\f6ca"}.fa-dashcube:before{content:"\f210"}.fa-database:before{content:"\f1c0"}.fa-deaf:before{content:"\f2a4"}.fa-delicious:before{content:"\f1a5"}.fa-democrat:before{content:"\f747"}.fa-deploydog:before{content:"\f38e"}.fa-deskpro:before{content:"\f38f"}.fa-desktop:before{content:"\f108...

\f38b"}.fa-cube:before{content:"\f1b2"}.fa-cubes:before{content:"\f1b3"}.fa-cut:before{content:"\f0c4"}.fa-cuttlefish:before{content:"\f38c"}.fa-d-and-d:before{content:"\f38d"}.fa-d-and-d-beyond:before{content:"\f6ca"}.fa-dashcube:before{content:"\f210"}.fa-database:before{content:"\f1c0"}.fa-deaf:before{content:"\f2a4"}.fa-delicious:before{content:"\f1a5"}.fa-democrat:before{content:"\f747"}.fa-deploydog:before{content:"\f38e"}.fa-deskpro:before{content:"\f38f"}.fa-desktop:before{content:"\f108...

    <glob pattern="*.fhc"/>
    <glob pattern="*.fh4"/>
    <glob pattern="*.fh40"/>
    <glob pattern="*.fh5"/>
    <glob pattern="*.fh50"/>
    <glob pattern="*.fh7"/>
    <glob pattern="*.fh8"/>
    <glob pattern="*.fh9"/>
    <glob pattern="*.fh10"/>
    <glob pattern="*.fh11"/>
    <glob pattern="*.fh12"/>
    <glob pattern="*.ft7"/>
    <glob pattern="*.ft8"/>
    <glob pattern="*.ft9"/>

	VFADDVV		V1, V2, V3			// d7912002
	VFADDVV		V1, V2, V0, V3			// d7912000
	VFADDVF		F10, V2, V3			// d7512502
	VFADDVF		F10, V2, V0, V3			// d7512500
	VFSUBVV		V1, V2, V3			// d791200a
	VFSUBVV		V1, V2, V0, V3			// d7912008
	VFSUBVF		F10, V2, V3			// d751250a
	VFSUBVF		F10, V2, V0, V3			// d7512508
	VFRSUBVF	F10, V2, V3			// d751259e
	VFRSUBVF	F10, V2, V0, V3			// d751259c

	VFADDVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
	VFSUBVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
	VFSUBVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
	VFRSUBVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
	VFWADDVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
	VFWADDVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"

	register["FS6"] = riscv.REG_FS6
	register["FS7"] = riscv.REG_FS7
	register["FS8"] = riscv.REG_FS8
	register["FS9"] = riscv.REG_FS9
	register["FS10"] = riscv.REG_FS10
	register["FS11"] = riscv.REG_FS11
	register["FT8"] = riscv.REG_FT8
	register["FT9"] = riscv.REG_FT9
	register["FT10"] = riscv.REG_FT10
	register["FT11"] = riscv.REG_FT11

	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP

	FNMSUBS F14, F16, F27, F14                 // 6ec32e1f
	FNMSUBD F29, F25, F8, F10                  // 0ae57d1f
	FNMULS F24, F22, F18                       // d28a381e
	FNMULD F14, F30, F7                        // c78b6e1e
	//TODO FRECPE F9, F2                       // 22d9e15e
	//TODO VFRECPE V0.S2, V28.S2               // 1cd8a10e
	//TODO FRECPS F28, F10, F9                 // 49fd3c5e
	//TODO VFRECPS V27.D2, V12.D2, V24.D2      // 98fd7b4e

	MOVF.S	F9, 0xfff0(R4)     // ERROR "invalid .S suffix"
	ADDF.S	F1, F2, F3         // ERROR "invalid .S suffix"
	SUBD.U	F1, F2             // ERROR "invalid .U suffix"
	NEGF.W	F9, F10            // ERROR "invalid .W suffix"
	ABSD.P	F9, F10            // ERROR "invalid .P suffix"
	MOVW.S	FPSR, R0           // ERROR "invalid .S suffix"
	MOVW.P	g, FPSR            // ERROR "invalid .P suffix"

	{"R15", "R15"},
	{"F0", "F0"},
	{"F1", "F1"},
	{"F2", "F2"},
	{"F3", "F3"},
	{"F4", "F4"},
	{"F5", "F5"},
	{"F6", "F6"},
	{"F7", "F7"},
	{"F8", "F8"},
	{"F9", "F9"},
	{"F10", "F10"},
	{"F11", "F11"},
	{"F12", "F12"},
	{"F13", "F13"},
	{"F14", "F14"},
	{"F15", "F15"},
	{"V0", "V0"},
	{"V1", "V1"},
	{"V2", "V2"},
	{"V3", "V3"},
	{"V4", "V4"},
	{"V5", "V5"},

	VMVXS		V2, V1				// ERROR "expected integer register in rd position"
	VMVSX		X11, X10			// ERROR "expected vector register in vd position"
	VMVSX		V2, V1				// ERROR "expected integer register in rs2 position"
	VFMVFS		X10, F10			// ERROR "expected vector register in vs2 position"
	VFMVFS		V2, V1				// ERROR "expected float register in rd position"
	VFMVSF		X10, V2				// ERROR "expected float register in rs2 position"