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Results 1 - 10 of 16 for R0 (0.01 sec)
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src/cmd/asm/internal/asm/testdata/armerror.s
MOVB F0, R0 // ERROR "illegal combination" MOVH F0, R0 // ERROR "illegal combination" MOVB R0, F0 // ERROR "illegal combination" MOVH R0, F0 // ERROR "illegal combination" MOVB R0>>0(R1), R2 // ERROR "bad shift" MOVB R0->0(R1), R2 // ERROR "bad shift" MOVB R0@>0(R1), R2 // ERROR "bad shift" MOVBS R0>>0(R1), R2 // ERROR "bad shift"
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Oct 23 15:18:14 UTC 2024 - 14.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/operand_test.go
{"$0", "$0"}, {"$256", "$256"}, {"(R0)", "(R0)"}, {"(R11)", "(R11)"}, {"(g)", "(g)"}, {"-12(R4)", "-12(R4)"}, {"0(PC)", "0(PC)"}, {"1024", "1024"}, {"12(R(1))", "12(R1)"}, {"12(R13)", "12(R13)"}, {"R0", "R0"}, {"R0->(32-1)", "R0->31"}, {"R0<<R1", "R0<<R1"}, {"R0>>R(1)", "R0>>R1"}, {"R0@>(32-1)", "R0@>31"}, {"R1", "R1"}, {"R11", "R11"}, {"R12", "R12"},
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Aug 29 18:31:05 UTC 2023 - 23.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
ADRP 12(PC), R2 // 02000090 // LDP/STP LDP (R0), (R0, R1) // 000440a9 LDP (R0), (R1, R2) // 010840a9 LDP 8(R0), (R1, R2) // 018840a9 LDP -8(R0), (R1, R2) // 01887fa9 LDP 11(R0), (R1, R2) // 1b2c0091610b40a9 LDP 1024(R0), (R1, R2) // 1b001091610b40a9 LDP.W 8(R0), (R1, R2) // 0188c0a9 LDP.P 8(R0), (R1, R2) // 0188c0a8 LDP (RSP), (R1, R2) // e10b40a9
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Jul 24 18:45:14 UTC 2024 - 95.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
AND R0->28, R1 // 401e01e0 AND R0@>28, R1 // 601e01e0 AND.S R0<<28, R1 // 001e11e0 AND.S R0>>28, R1 // 201e11e0 AND.S R0->28, R1 // 401e11e0 AND.S R0@>28, R1 // 601e11e0 AND R0<<R1, R2, R3 // 103102e0 AND R0>>R1, R2, R3 // 303102e0 AND R0->R1, R2, R3 // 503102e0 AND R0@>R1, R2, R3 // 703102e0 AND.S R0<<R1, R2, R3 // 103112e0
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
android/guava-tests/test/com/google/common/util/concurrent/RateLimiterTest.java
limiter.acquire(); // #7 } assertEvents( "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #1 "U0.50", // #2 "U4.00", // #3 "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #4 "U0.50", // #5 "U2.00", // #6 "R0.00, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50"); // #7 } public void testWarmUpWithColdFactor() {
Registered: Fri Nov 01 12:43:10 UTC 2024 - Last Modified: Mon Oct 21 14:28:19 UTC 2024 - 21.8K bytes - Viewed (0) -
guava-tests/test/com/google/common/util/concurrent/RateLimiterTest.java
limiter.acquire(); // #7 } assertEvents( "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #1 "U0.50", // #2 "U4.00", // #3 "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #4 "U0.50", // #5 "U2.00", // #6 "R0.00, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50"); // #7 } public void testWarmUpWithColdFactor() {
Registered: Fri Nov 01 12:43:10 UTC 2024 - Last Modified: Mon Oct 21 14:28:19 UTC 2024 - 21.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
CMP R3, R0 // 7c230000 CMP R3, R0, CR1 // CMP R3,CR1,R0 // 7ca30000 CMPU R3, R4 // 7c232040 CMPU R3, R0 // 7c230040 CMPU R3, R0, CR2 // CMPU R3,CR2,R0 // 7d230040 CMPW R3, R4 // 7c032000 CMPW R3, R0 // 7c030000 CMPW R3, R0, CR3 // CMPW R3,CR3,R0 // 7d830000
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Oct 29 13:14:38 UTC 2024 - 51K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
CRC32CB R19, R27, R22 // 7653d31a CRC32CH R21, R0, R20 // 1454d51a CRC32CW R9, R3, R21 // 7558c91a CRC32CX R11, R0, R24 // 185ccb9a CSELW LO, R4, R20, R12 // 8c30941a CSEL GE, R0, R12, R14 // 0ea08c9a CSETW GE, R3 // e3b79f1a
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
doc/asm.html
</li> <li> <code>(R2)(R0)</code>: The location at <code>R0</code> plus <code>R2</code>. </li> <li> <code>R0.UXTB</code> <br> <code>R0.UXTB<<imm</code>: <code>UXTB</code>: extract an 8-bit value from the low-order bits of <code>R0</code> and zero-extend it to the size of <code>R0</code>. <code>R0.UXTB<<imm</code>: left shift the result of <code>R0.UXTB</code> by <code>imm</code> bits.
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Nov 28 19:15:27 UTC 2023 - 36.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
RXSBGT $17, $8, $16, R9, R10 // eca991081057 ROSBGT $9, $24, $11, R11, R0 // ec0b89180b56 RISBG $0, $31, $32, R1, R2 // ec21001f2055 RISBGN $17, $8, $16, R3, R4 // ec4311081059 RISBGZ $9, $24, $11, R5, R6 // ec6509980b55 RISBGNZ $0, $31, $32, R7, R8 // ec87009f2059 RISBHG $17, $8, $16, R9, R10 // eca91108105d RISBLG $9, $24, $11, R11, R0 // ec0b09180b51 RISBHGZ $17, $8, $16, R9, R10 // eca91188105d
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Sep 18 15:49:24 UTC 2024 - 22.1K bytes - Viewed (0)