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Results 21 - 30 of 38 for SRL (0.05 sec)
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src/main/java/org/codelibs/fess/es/user/allcommon/EsAbstractConditionQuery.java
import org.dbflute.dbmeta.info.ColumnInfo; import org.dbflute.dbmeta.name.ColumnRealName; import org.dbflute.dbmeta.name.ColumnSqlName; import org.dbflute.exception.InvalidQueryRegisteredException; import org.dbflute.util.Srl; import org.opensearch.common.unit.Fuzziness; import org.opensearch.index.query.BoolQueryBuilder; import org.opensearch.index.query.CommonTermsQueryBuilder; import org.opensearch.index.query.ExistsQueryBuilder;
Registered: Wed Jun 12 13:08:18 UTC 2024 - Last Modified: Thu Feb 22 01:37:57 UTC 2024 - 21.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
// unsigned right shift (Rsh64Ux(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRL <t> x y) (Rsh32Ux(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRL <t> (ZeroExt32to64 x) y) (Rsh16Ux(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRL <t> (ZeroExt16to64 x) y) (Rsh8Ux(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRL <t> (ZeroExt8to64 x) y) // shift value may be out of range, use CMP + CSEL instead
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPSOps.go
{name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int32"}, // arg0 << auxInt, shift amount must be 0 through 31 inclusive {name: "SRL", argLength: 2, reg: gp21, asm: "SRL"}, // arg0 >> arg1, unsigned, shift amount is mod 32 {name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int32"}, // arg0 >> auxInt, shift amount must be 0 through 31 inclusive
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 24K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteRISCV64.go
v.AuxInt = int64ToAuxInt(int64(val & 31)) v.AddArg(x) return true } return false } func rewriteValueRISCV64_OpRISCV64SRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SRL x (MOVDconst [val])) // result: (SRLI [int64(val&63)] x) for { x := v_0 if v_1.Op != OpRISCV64MOVDconst { break } val := auxIntToInt64(v_1.AuxInt) v.reset(OpRISCV64SRLI)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 205.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM.go
v0.AddArg3(x, y, z) v.AddArg(v0) return true } // match: (CMP x (SRL y z)) // result: (CMPshiftRLreg x y z) for { x := v_0 if v_1.Op != OpARMSRL { break } z := v_1.Args[1] y := v_1.Args[0] v.reset(OpARMCMPshiftRLreg) v.AddArg3(x, y, z) return true } // match: (CMP (SRL y z) x) // result: (InvertFlags (CMPshiftRLreg x y z)) for {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 486.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
{name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int32"}, // arg0 << auxInt, 0 <= auxInt < 32 {name: "SRL", argLength: 2, reg: gp21, asm: "SRL"}, // arg0 >> arg1, unsigned, shift amount is mod 256 {name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int32"}, // arg0 >> auxInt, unsigned, 0 <= auxInt < 32
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0) -
src/cmd/link/internal/mips64/asm.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 23 05:58:20 UTC 2023 - 11K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
{name: "SRAW", argLength: 2, reg: gp21, asm: "SRAW"}, // arg0 >> (aux1 & 31), arithmetic right shift of 32 bit value, sign extended to 64 bits {name: "SRL", argLength: 2, reg: gp21, asm: "SRL"}, // arg0 >> (aux1 & 63), logical right shift {name: "SRLW", argLength: 2, reg: gp21, asm: "SRLW"}, // arg0 >> (aux1 & 31), logical right shift of 32 bit value, sign extended to 64 bits
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 30.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteCond_test.go
one64 int64 = 1 one32 int32 = 1 v64 int64 = 11 // ensure it's not 2**n +/- 1 v64_n int64 = -11 v32 int32 = 11 v32_n int32 = -11 uv32 uint32 = 19 uz uint8 = 1 // for lowering to SLL/SRL/SRA ) var crTests = []struct { name string tf func(t *testing.T) }{ {"AddConst64", testAddConst64}, {"AddConst32", testAddConst32}, {"AddVar64", testAddVar64}, {"AddVar64Cset", testAddVar64Cset},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 24 01:19:09 UTC 2023 - 11.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM64.go
v_0 := v.Args[0] // match: (SRL x (MOVDconst [c])) // result: (SRLconst x [c&63]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(c & 63) v.AddArg(x) return true } // match: (SRL x (ANDconst [63] y)) // result: (SRL x y) for { x := v_0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 608.6K bytes - Viewed (0)