ADDQ R8, R9 ADCQ R15, R10 ADCQ AX, R11 ADCQ DX, R12 XORQ R13, R13 // Second stage MOVQ R9, AX MOVQ R9, R15 SHLQ $0x20, R9 MULQ p256const1<>+0(SB) SHRQ $0x20, R15 ADDQ R9, R10 ADCQ R15, R11 ADCQ AX, R12 ADCQ DX, R13 XORQ R8, R8 // Third stage MOVQ R10, AX MOVQ R10, R15 SHLQ $0x20, R10 MULQ p256const1<>+0(SB) SHRQ $0x20, R15 ADDQ R10, R11 ADCQ R15, R12 ADCQ AX, R13 ADCQ DX, R8 XORQ R9, R9 // Last stage MOVQ R11, AX MOVQ R11, R15 SHLQ $0x20, R11 MULQ p256const1<>+0(SB) SHRQ $0x20, R15 ADDQ R11, R12 ADCQ...

	VLD1R.P	(R15)(R1), [V15.H4]                             // efc5c10d
	VLD2R	(R15), [V15.H4, V16.H4]                         // efc5600d
	VLD2R.P	16(R0), [V0.D2, V1.D2]                          // 00ccff4d
	VLD2R.P	(R0)(R5), [V31.D1, V0.D1]                       // 1fcce50d
	VLD3R	(RSP), [V31.S2, V0.S2, V1.S2]                   // ffeb400d
	VLD3R.P	6(R15), [V15.H4, V16.H4, V17.H4]                // efe5df0d

        // Act
        byte[] r14 = NtlmUtil.getPreNTLMResponse(cifsContext, password14, challenge);
        byte[] r15 = NtlmUtil.getPreNTLMResponse(cifsContext, password15, challenge);

        // Assert: equal because only first 14 OEM bytes are used
        assertArrayEquals(r14, r15, "Only first 14 OEM bytes affect Pre-NTLM response");
        assertEquals(24, r14.length);

        // Verify collaborator interactions

	}
	if name[0] != 'R' {
		p.errorf("expected g or R0 through R15; found %s", name)
		return 0
	}
	r, ok := p.registerReference(name)
	if !ok {
		return 0
	}
	reg := r - p.arch.Register["R0"]
	if reg < 0 {
		// Could happen for an architecture having other registers prefixed by R
		p.errorf("expected g or R0 through R15; found %s", name)
		return 0
	}
	return uint16(reg)
}

<code>&gt;&gt;</code> (logical right shift), and
<code>@&gt;</code> (rotate right).

</li>

<li>
<code>[R0,g,R12-R15]</code>: For multi-register instructions, the set comprising
<code>R0</code>, <code>g</code>, and <code>R12</code> through <code>R15</code> inclusive.
</li>

<li>
<code>(R5, R6)</code>: Destination register pair.
</li>

</ul>

<h3 id="arm64">ARM64</h3>

	MRS	PMSWINC_EL0, R3                                  // ERROR "system register is not readable"
	MRS	OSLAR_EL1, R3                                    // ERROR "system register is not readable"
	VLD3R.P	24(R15), [V15.H4,V16.H4,V17.H4]                  // ERROR "invalid post-increment offset"
	VBIT	V1.H4, V12.H4, V3.H4                             // ERROR "invalid arrangement"

pkg debug/macho, type RegsAMD64 struct, R12 uint64
pkg debug/macho, type RegsAMD64 struct, R13 uint64
pkg debug/macho, type RegsAMD64 struct, R14 uint64
pkg debug/macho, type RegsAMD64 struct, R15 uint64
pkg debug/macho, type RegsAMD64 struct, R8 uint64
pkg debug/macho, type RegsAMD64 struct, R9 uint64
pkg debug/macho, type RegsAMD64 struct, SI uint64
pkg debug/macho, type RegsAMD64 struct, SP uint64