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Results 21 - 30 of 156 for fabs (0.1 sec)

  1. src/cmd/internal/obj/loong64/asm.go

    	case 32: // fadd fr1,[fr2],fr3
    		r := int(p.Reg)
    		if r == 0 {
    			r = int(p.To.Reg)
    		}
    		o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
    
    	case 33: // fabs fr1, fr3
    		o1 = OP_RRR(c.oprrr(p.As), uint32(0), uint32(p.From.Reg), uint32(p.To.Reg))
    
    	case 34: // mov $con,fr
    		v := c.regoff(&p.From)
    		a := AADDU
    		if o.from1 == C_ANDCON {
    			a = AOR
    		}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 61.8K bytes
    - Viewed (0)
  2. src/cmd/gofmt/testdata/tabs.input

    Daniel Martí <******@****.***> 1652048963 +0100
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 10 19:22:49 UTC 2022
    - 449 bytes
    - Viewed (0)
  3. src/cmd/gofmt/testdata/tabs.golden

    Daniel Martí <******@****.***> 1652048963 +0100
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 10 19:22:49 UTC 2022
    - 480 bytes
    - Viewed (0)
  4. src/cmd/internal/obj/riscv/anames.go

    	"BEXTI",
    	"BINV",
    	"BINVI",
    	"BSET",
    	"BSETI",
    	"WORD",
    	"BEQZ",
    	"BGEZ",
    	"BGT",
    	"BGTU",
    	"BGTZ",
    	"BLE",
    	"BLEU",
    	"BLEZ",
    	"BLTZ",
    	"BNEZ",
    	"FABSD",
    	"FABSS",
    	"FNEGD",
    	"FNEGS",
    	"FNED",
    	"FNES",
    	"MOV",
    	"MOVB",
    	"MOVBU",
    	"MOVF",
    	"MOVD",
    	"MOVH",
    	"MOVHU",
    	"MOVW",
    	"MOVWU",
    	"NEG",
    	"NEGW",
    	"NOT",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/lite/schema/schema.fbs

      REDUCE_ANY = 91,
      SQUARE = 92,
      ZEROS_LIKE = 93,
      FILL = 94,
      FLOOR_MOD = 95,
      RANGE = 96,
      RESIZE_NEAREST_NEIGHBOR = 97,
      LEAKY_RELU = 98,
      SQUARED_DIFFERENCE = 99,
      MIRROR_PAD = 100,
      ABS = 101,
      SPLIT_V = 102,
      UNIQUE = 103,
      CEIL = 104,
      REVERSE_V2 = 105,
      ADD_N = 106,
      GATHER_ND = 107,
      COS = 108,
      WHERE = 109,
      RANK = 110,
      ELU = 111,
      REVERSE_SEQUENCE = 112,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri May 03 18:01:23 UTC 2024
    - 41.7K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/lite/schema/schema_v3b.fbs

      REDUCE_ANY = 91,
      SQUARE = 92,
      ZEROS_LIKE = 93,
      FILL = 94,
      FLOOR_MOD = 95,
      RANGE = 96,
      RESIZE_NEAREST_NEIGHBOR = 97,
      LEAKY_RELU = 98,
      SQUARED_DIFFERENCE = 99,
      MIRROR_PAD = 100,
      ABS = 101,
      SPLIT_V = 102,
      UNIQUE = 103,
      CEIL = 104,
      REVERSE_V2 = 105,
      ADD_N = 106,
      GATHER_ND = 107,
      COS = 108,
      WHERE = 109,
      RANK = 110,
      ELU = 111,
      REVERSE_SEQUENCE = 112,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue May 28 14:28:27 UTC 2024
    - 30K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/rewritePPC64.go

    }
    func rewriteValuePPC64_OpPPC64FNEG(v *Value) bool {
    	v_0 := v.Args[0]
    	// match: (FNEG (FABS x))
    	// result: (FNABS x)
    	for {
    		if v_0.Op != OpPPC64FABS {
    			break
    		}
    		x := v_0.Args[0]
    		v.reset(OpPPC64FNABS)
    		v.AddArg(x)
    		return true
    	}
    	// match: (FNEG (FNABS x))
    	// result: (FABS x)
    	for {
    		if v_0.Op != OpPPC64FNABS {
    			break
    		}
    		x := v_0.Args[0]
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 360.2K bytes
    - Viewed (0)
  8. src/math/floor_riscv64.s

    	MOVD	x+0(FP), F0; 	\
    	/* whether x is NaN */; \
    	FEQD	F0, F0, X6;	\
    	BNEZ	X6, 3(PC);	\
    	/* return NaN if x is NaN */; \
    	MOVD	F0, ret+8(FP); 	\
    	RET;			\
    	MOV	$PosInf, X6;	\
    	FMVDX	X6, F1;		\
    	FABSD	F0, F2;		\
    	/* if abs(x) > +Inf, return Inf instead of round(x) */; \
    	FLTD	F1, F2, X6;	\
    	/* Inf should keep same signed with x then return */;	\
    	BEQZ	X6, 3(PC); \
    	FCVTLD.MODE	F0, X6;	\
    	FCVTDL	X6, F1;		\
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 23 08:34:12 UTC 2024
    - 1K bytes
    - Viewed (0)
  9. src/math/big/rat.go

    		// a squared Rat is positive and can't be reduced (no need to call norm())
    		z.a.neg = false
    		z.a.abs = z.a.abs.sqr(x.a.abs)
    		if len(x.b.abs) == 0 {
    			z.b.abs = z.b.abs.setWord(1)
    		} else {
    			z.b.abs = z.b.abs.sqr(x.b.abs)
    		}
    		return z
    	}
    	z.a.Mul(&x.a, &y.a)
    	z.b.abs = mulDenom(z.b.abs, x.b.abs, y.b.abs)
    	return z.norm()
    }
    
    // Quo sets z to the quotient x/y and returns z.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 11:59:09 UTC 2023
    - 13.5K bytes
    - Viewed (0)
  10. src/cmd/internal/obj/ppc64/asm9.go

    	{as: AFADD, a1: C_FREG, a6: C_FREG, type_: 2, size: 4},
    	{as: AFADD, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 2, size: 4},
    	{as: AFABS, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
    	{as: AFABS, a6: C_FREG, type_: 33, size: 4},
    	{as: AFMADD, a1: C_FREG, a2: C_FREG, a3: C_FREG, a6: C_FREG, type_: 34, size: 4},
    	{as: AFMUL, a1: C_FREG, a6: C_FREG, type_: 32, size: 4},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 13:55:28 UTC 2024
    - 156.1K bytes
    - Viewed (0)
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