Search Options

Results per page
Sort
Preferred Languages
Advance

Results 11 - 20 of 157 for fabs (0.07 sec)

  1. src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/plan9x.go

    				} else if rno >= uint16(S0) && rno <= uint16(S31) {
    					op = fmt.Sprintf("%sS", op)
    				} else if rno >= uint16(D0) && rno <= uint16(D31) {
    					op = fmt.Sprintf("%sD", op)
    				}
    			}
    		}
    
    	case FABS, FNEG, FSQRT, FRINTN, FRINTP, FRINTM, FRINTZ, FRINTA, FRINTX, FRINTI:
    		if r, ok := inst.Args[1].(Reg); ok {
    			rno := uint16(r)
    			if rno >= uint16(S0) && rno <= uint16(S31) {
    				op = fmt.Sprintf("%sS", op)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 16 22:24:28 UTC 2022
    - 17K bytes
    - Viewed (0)
  2. src/math/all_test.go

    		}
    	}
    }
    
    func TestAbs(t *testing.T) {
    	for i := 0; i < len(vf); i++ {
    		if f := Abs(vf[i]); fabs[i] != f {
    			t.Errorf("Abs(%g) = %g, want %g", vf[i], f, fabs[i])
    		}
    	}
    	for i := 0; i < len(vffabsSC); i++ {
    		if f := Abs(vffabsSC[i]); !alike(fabsSC[i], f) {
    			t.Errorf("Abs(%g) = %g, want %g", vffabsSC[i], f, fabsSC[i])
    		}
    	}
    }
    
    func TestDim(t *testing.T) {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jul 07 17:39:26 UTC 2023
    - 86.8K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    // A particular pattern seen in cgo code:
    (AND (MOVDconst [c]) x:(MOVBZload _ _)) => (ANDconst [c&0xFF] x)
    
    // floating point negative abs
    (FNEG (F(ABS|NABS) x)) => (F(NABS|ABS) x)
    
    // floating-point fused multiply-add/sub
    (F(ADD|SUB) (FMUL x y) z) && x.Block.Func.useFMA(v) => (FM(ADD|SUB) x y z)
    (F(ADDS|SUBS) (FMULS x y) z) && x.Block.Func.useFMA(v) => (FM(ADDS|SUBS) x y z)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/quantization/common/quantization_lib/quantization_utils.cc

          maxs[i] = std::max(maxs[i], 0.0);
          mins[i] = std::min(mins[i], 0.0);
        }
        if (symmetric) {
          for (int i = 0; i < dim_size; ++i) {
            maxs[i] = std::max(std::abs(mins[i]), std::abs(maxs[i]));
            mins[i] = -maxs[i];
          }
        }
      }
    }
    
    Type GetUniformQuantizedTypeForWeight(
        const ElementsAttr attr, const bool symmetric, const unsigned num_bits,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed May 08 02:10:16 UTC 2024
    - 43.2K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/quantization/common/quantization_lib/quantization_utils.h

                                  double& max) const {
        double range = std::fabs(max - min);
        if (num_bits <= 8 && range >= 10.0) {
          op.emitWarning()
              << "Tensor range is too wide to be quantized. Use tf.clip_by_value "
                 "or tf.relu6 to narrow the tensor range. Range: "
              << range << ", bit width: " << num_bits;
        }
        if (std::abs(max - min) < kNearZeroTolerance) {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Apr 24 20:30:06 UTC 2024
    - 41.7K bytes
    - Viewed (0)
  6. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go

    	CRORC:          "crorc",
    	CRXOR:          "crxor",
    	DCBZ:           "dcbz",
    	EQV:            "eqv",
    	EQVCC:          "eqv.",
    	EXTSH:          "extsh",
    	EXTSHCC:        "extsh.",
    	FABS:           "fabs",
    	FABSCC:         "fabs.",
    	FADD:           "fadd",
    	FADDCC:         "fadd.",
    	FCMPO:          "fcmpo",
    	FCMPU:          "fcmpu",
    	FDIV:           "fdiv",
    	FDIVCC:         "fdiv.",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 334.7K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/asm/testdata/ppc64.s

    	FNMSUBS F1, F2, F3, F4          // ec8110fc
    	FNMSUBSCC F1, F2, F3, F4        // ec8110fd
    	FSEL F1, F2, F3, F4             // fc8110ee
    	FSELCC F1, F2, F3, F4           // fc8110ef
    	FABS F1, F2                     // fc400a10
    	FNABS F1, F2                    // fc400910
    	FABSCC F1, F2                   // fc400a11
    	FNABSCC F1, F2                  // fc400911
    	FNEG F1, F2                     // fc400850
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
  8. src/cmd/vendor/golang.org/x/arch/x86/x86asm/tables.go

    	DIVSS:           "DIVSS",
    	DPPD:            "DPPD",
    	DPPS:            "DPPS",
    	EMMS:            "EMMS",
    	ENTER:           "ENTER",
    	EXTRACTPS:       "EXTRACTPS",
    	F2XM1:           "F2XM1",
    	FABS:            "FABS",
    	FADD:            "FADD",
    	FADDP:           "FADDP",
    	FBLD:            "FBLD",
    	FBSTP:           "FBSTP",
    	FCHS:            "FCHS",
    	FCMOVB:          "FCMOVB",
    	FCMOVBE:         "FCMOVBE",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 16 22:24:28 UTC 2022
    - 266.8K bytes
    - Viewed (0)
  9. src/math/abs.go

    // Use of this source code is governed by a BSD-style
    // license that can be found in the LICENSE file.
    
    package math
    
    // Abs returns the absolute value of x.
    //
    // Special cases are:
    //
    //	Abs(±Inf) = +Inf
    //	Abs(NaN) = NaN
    func Abs(x float64) float64 {
    	return Float64frombits(Float64bits(x) &^ (1 << 63))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 11 16:34:30 UTC 2022
    - 366 bytes
    - Viewed (0)
  10. src/cmd/internal/obj/mips/asm0.go

    	case 32: /* fadd fr1,[fr2],fr3 */
    		r := p.Reg
    		if r == obj.REG_NONE {
    			r = p.To.Reg
    		}
    		o1 = OP_FRRR(c.oprrr(p.As), p.From.Reg, r, p.To.Reg)
    
    	case 33: /* fabs fr1, fr3 */
    		o1 = OP_FRRR(c.oprrr(p.As), obj.REG_NONE, p.From.Reg, p.To.Reg)
    
    	case 34: /* mov $con,fr ==> or/add $i,t; mov t,fr */
    		a := AADDU
    		if o.a1 == C_ANDCON {
    			a = AOR
    		}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 17:46:09 UTC 2024
    - 53.6K bytes
    - Viewed (0)
Back to top