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Results 11 - 19 of 19 for mfvscr (0.15 sec)
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src/cmd/internal/obj/ppc64/asm9.go
v = c.regoff(p.GetFrom3()) & 255 } else { v = 255 } o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11 case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */ if p.To.Reg == 0 { c.ctxt.Diag("must specify FPSCR(n)\n%v", p) } o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12 case 66: /* mov spr,r1; mov r1,spr */ var r int var v int32
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go
startArg = 1 case 9: buf.WriteString("ctr") startArg = 1 default: buf.WriteString("spr") } default: buf.WriteString("spr") } case "mfspr": opcode := inst.Op.String() buf.WriteString(opcode[0:2]) arg := inst.Args[0] switch spr := inst.Args[1].(type) { case SpReg: switch spr { case 1: buf.WriteString("xer ")
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 12.2K bytes - Viewed (0) -
src/hash/crc32/crc32_ppc64le.s
VSLDOI $8,V0,zeroes,V0 #else VAND V0,mask_32bit,V1 VPMSUMD V1,const1,V1 VAND V1,mask_32bit,V1 VPMSUMD V1,const2,V1 VXOR V0,V1,V0 VSLDOI $4,V0,zeroes,V0 #endif MFVSRD VS32,R3 // VS32 = V0 NOR R3,R3,R3 // return ^crc MOVW R3,ret+32(FP) RET first_warm_up_done: LVX (R3),const1 ADD $16,R3 VPMSUMD V16,const1,V8 VPMSUMD V17,const1,V9
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 06 12:09:50 UTC 2024 - 13.1K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/a.out.go
C_SOREG /* An $n+reg memory arg where n is a 16 bit signed offset */ C_LOREG /* An $n+reg memory arg where n is a 32 bit signed offset */ C_XOREG /* An reg+reg memory arg */ C_FPSCR /* The fpscr register */ C_LR /* The link register */ C_CTR /* The count register */ C_ANY /* Any argument */ C_GOK /* A non-matched argument */ C_ADDR /* A symbolic memory location */
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
// There are optimizations that should apply -- (Xi2f64 (MOVWload (not-ADD-ptr+offset) ) ) could use // the word-load instructions. (Xi2f64 (MOVDload ptr )) can be (FMOVDload ptr) {name: "MFVSRD", argLength: 1, reg: fpgp, asm: "MFVSRD", typ: "Int64"}, // move 64 bits of F register into G register {name: "MTVSRD", argLength: 1, reg: gpfp, asm: "MTVSRD", typ: "Float64"}, // move 64 bits of G register into F register
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/runtime/asm_arm.s
// disable runfast (flush-to-zero) mode of vfp if runtime.goarmsoftfp == 0 MOVB runtime·goarmsoftfp(SB), R11 CMP $0, R11 BNE 4(PC) WORD $0xeef1ba10 // vmrs r11, fpscr BIC $(1<<24), R11 WORD $0xeee1ba10 // vmsr fpscr, r11 RET TEXT runtime·mstart(SB),NOSPLIT|TOPFRAME,$0 BL runtime·mstart0(SB) RET // not reached /* * go-routine */ // void gogo(Gobuf*)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 23 21:00:52 UTC 2024 - 32.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
LXSIWZX (R3), VS1 // 7c201818 STXSIWX VS1, (R3)(R4) // 7c241918 STXSIWX VS1, (R3)(R0) // 7c201918 STXSIWX VS1, (R3) // 7c201918 MFVSRD VS1, R3 // 7c230066 MTFPRD R3, F0 // 7c030166 MFVRD V0, R3 // 7c030067 MFVSRLD VS63,R4 // 7fe40267 MFVSRLD V31,R4 // 7fe40267
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
b := v.Block typ := &b.Func.Config.Types // match: (MFVSRD (FMOVDconst [c])) // result: (MOVDconst [int64(math.Float64bits(c))]) for { if v_0.Op != OpPPC64FMOVDconst { break } c := auxIntToFloat64(v_0.AuxInt) v.reset(OpPPC64MOVDconst) v.AuxInt = int64ToAuxInt(int64(math.Float64bits(c))) return true } // match: (MFVSRD x:(FMOVDload [off] {sym} ptr mem))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MFVSRD", argLen: 1, asm: ppc64.AMFVSRD, reg: regInfo{ inputs: []inputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)