VPDPWSSD -7(CX)(DX*4), Y2, K3, Y14                 // 62726d2b52b491f9ffffff
	VPDPWSSD Y8, Y22, K3, Y14                          // 62524d2352f0
	VPDPWSSD Y9, Y22, K3, Y14                          // 62524d2352f1
	VPDPWSSD Y22, Y22, K3, Y14                         // 62324d2352f6
	VPDPWSSD 15(R8)(R14*4), Y22, K3, Y14               // 62124d2352b4b00f000000

	V4FNMADDPS 99(R15)(R15*1), [Z1-Z4], K3, Z15        // 6212774baabc3f63000000
	V4FNMADDPS (DX), [Z1-Z4], K3, Z15                  // 6272774baa3a
	V4FNMADDPS 99(R15)(R15*1), [Z11-Z14], K3, Z15      // 6212274baabc3f63000000
	V4FNMADDPS (DX), [Z11-Z14], K3, Z15                // 6272274baa3a
	V4FNMADDPS 99(R15)(R15*1), [Z21-Z24], K3, Z15      // 62125743aabc3f63000000
	V4FNMADDPS (DX), [Z21-Z24], K3, Z15                // 62725743aa3a

	ADDL -2147483648(AX), AX // 038000000080
	// Make sure MOV CR/DR continues to work after changing its movtabs.
	MOVL CR0, AX // 0f20c0
	MOVL CR0, DX // 0f20c2
	MOVL CR4, DI // 0f20e7
	MOVL AX, CR0 // 0f22c0
	MOVL DX, CR0 // 0f22c2
	MOVL DI, CR4 // 0f22e7
	MOVL DR0, AX // 0f21c0
	MOVL DR6, DX // 0f21f2
	MOVL DR7, SI // 0f21fe
	// Test other movtab entries.
	PUSHL SS // 16
	PUSHL FS // 0fa0
	POPL FS  // 0fa1
	POPL SS  // 17

	VPGATHERDQ X2, 664(BX*1), X1    // ERROR "invalid instruction"
	VPGATHERDQ Y2, (BP)(AX*2), Y1   // ERROR "invalid instruction"
	VPGATHERDQ Y5, 664(DX*8), Y6    // ERROR "invalid instruction"
	VPGATHERDQ Y5, (DX), Y0         // ERROR "invalid instruction"
	// VM/X rejects Y index register.
	VPGATHERDQ Y5, 664(Y14*8), Y6   // ERROR "invalid instruction"

		lines(
			"#define LOAD(off, reg) \\",
			"\tMOVBLZX	(off*4)(R12),	reg \\",
			"\tADDB	reg,		DX",
			"",
			"LOAD(8, AX)",
		),
		"\n.\n.MOVBLZX.(.8.*.4.).(.R12.).,.AX.\n.ADDB.AX.,.DX.\n",
	},
	{
		"nested multiline macro",
		lines(
			"#define KEYROUND(xmm, load, off, r1, r2, index) \\",
			"\tMOVBLZX	(BP)(DX*4),	R8 \\",
			"\tload((off+1), r2) \\",
			"\tMOVB	R8,		(off*4)(R12) \\",

				}
			}
			if tok == scanner.EOF {
				p.errorf("unexpected EOF")
				return "", "", nil, false
			}
			// Split operands on comma. Also, the old syntax on x86 for a "register pair"
			// was AX:DX, for which the new syntax is DX, AX. Note the reordering.
			if tok == '\n' || tok == ';' || (nesting == 0 && (tok == ',' || tok == ':')) {
				if tok == ':' {
					// Remember this location so we can swap the operands below.

	PINSRD	$1, (AX), X0
	PINSRD	$2, foo+4(FP), X0

// Was bug: LOOP is a branch instruction.
	JCS	2(PC)
loop:
	LOOP	loop // LOOP

// Tests for TLS reference.
	MOVL    (TLS), AX
	MOVL    8(TLS), DX

// LTYPE0 nonnon	{ outcode(int($1), &$2); }
	RET

pkg debug/macho, type Regs386 struct, CX uint32
pkg debug/macho, type Regs386 struct, DI uint32
pkg debug/macho, type Regs386 struct, DS uint32
pkg debug/macho, type Regs386 struct, DX uint32
pkg debug/macho, type Regs386 struct, ES uint32
pkg debug/macho, type Regs386 struct, FLAGS uint32
pkg debug/macho, type Regs386 struct, FS uint32
pkg debug/macho, type Regs386 struct, GS uint32