MOVB    runtime·goarmsoftfp(SB), R11
	CMP	$0, R11
	BNE     skipfpsave
	MOVD	F8, (40+8*0)(R13)
	MOVD	F9, (40+8*1)(R13)
	MOVD	F10, (40+8*2)(R13)
	MOVD	F11, (40+8*3)(R13)
	MOVD	F12, (40+8*4)(R13)
	MOVD	F13, (40+8*5)(R13)
	MOVD	F14, (40+8*6)(R13)
	MOVD	F15, (40+8*7)(R13)
skipfpsave:
	// Save argc/argv.
	MOVW	R0, _rt0_arm_lib_argc<>(SB)
	MOVW	R1, _rt0_arm_lib_argv<>(SB)

	a0, a1, a2, a3 int
	f0, f1, f2, f3 float64
}

type StructFillRegs struct {
	a0, a1, a2, a3, a4, a5, a6, a7, a8                              int
	f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14 float64
}

func (m *StructWithMethods) AllRegsCall(s StructFewRegs, _ MagicLastTypeNameForTestingRegisterABI) StructFewRegs {
	m.Value = 1
	return s
}

	"R8",
	"R9",
	"R10",
	"R11",
	"R12",
	"g", // R13
	"R14",
	"SP", // R15
	"F0",
	"F1",
	"F2",
	"F3",
	"F4",
	"F5",
	"F6",
	"F7",
	"F8",
	"F9",
	"F10",
	"F11",
	"F12",
	"F13",
	"F14",
	"F15",

	// If you add registers, update asyncPreempt in runtime.

	//pseudo-registers
	"SB",
}

func init() {
	// Make map from reg names to reg integers.

	STP	(R14, R15), (14*8)(R20)
	FSTPD	(F0, F1), (16*8)(R20)
	FSTPD	(F2, F3), (18*8)(R20)
	FSTPD	(F4, F5), (20*8)(R20)
	FSTPD	(F6, F7), (22*8)(R20)
	FSTPD	(F8, F9), (24*8)(R20)
	FSTPD	(F10, F11), (26*8)(R20)
	FSTPD	(F12, F13), (28*8)(R20)
	FSTPD	(F14, F15), (30*8)(R20)
	RET

// unspillArgs loads args into registers from a *internal/abi.RegArgs in R20.
TEXT ·unspillArgs(SB),NOSPLIT,$0-0
	LDP	(0*8)(R20), (R0, R1)

		ParamIntRegNames: "X10 X11 X12 X13 X14 X15 X16 X17 X8 X9 X18 X19 X20 X21 X22 X23",
		// Float parameters passed in register F10-F17, F8-F9, F18-F23
		ParamFloatRegNames: "F10 F11 F12 F13 F14 F15 F16 F17 F8 F9 F18 F19 F20 F21 F22 F23",
	})

func f11c(a []int, i int) {
	useSlice(a[:i])
	useSlice(a[:i]) // ERROR "Proved IsSliceInBounds$"
}

func f11d(a []int, i int) {
	useInt(a[2*i+7])
	useInt(a[2*i+7]) // ERROR "Proved IsInBounds$"
}

func f12(a []int, b int) {
	useSlice(a[:b])
}

func f13a(a, b, c int, x bool) int {
	if a > 12 {
		if x {
			if a < 12 { // ERROR "Disproved Less64$"
				return 1
			}
		}
		if x {

	FMOVD   F4, 120(R20)
	FMOVD   F5, 128(R20)
	FMOVD   F6, 136(R20)
	FMOVD   F7, 144(R20)
	FMOVD   F8, 152(R20)
	FMOVD   F9, 160(R20)
	FMOVD   F10, 168(R20)
	FMOVD   F11, 176(R20)
	FMOVD   F12, 184(R20)
	RET

// unspillArgs loads args into registers from a *internal/abi.RegArgs in R20.
TEXT runtime·unspillArgs(SB),NOSPLIT,$0-0
	MOVD    0(R20), R3
	MOVD    8(R20), R4
	MOVD    16(R20), R5

	"F0":  REG_F0,
	"F1":  REG_F1,
	"F2":  REG_F2,
	"F3":  REG_F3,
	"F4":  REG_F4,
	"F5":  REG_F5,
	"F6":  REG_F6,
	"F7":  REG_F7,
	"F8":  REG_F8,
	"F9":  REG_F9,
	"F10": REG_F10,
	"F11": REG_F11,
	"F12": REG_F12,
	"F13": REG_F13,
	"F14": REG_F14,
	"F15": REG_F15,

	"F16": REG_F16,
	"F17": REG_F17,
	"F18": REG_F18,
	"F19": REG_F19,
	"F20": REG_F20,
	"F21": REG_F21,
	"F22": REG_F22,
	"F23": REG_F23,

		ID  uint
		F1  string
		F2  string
		F3  string
		F4  string
		F5  string
		F6  string
		F7  string
		F8  string
		F9  string
		F10 string
		F11 string
		F12 string
		F13 string
		F14 string
		F15 string
		F16 string
		F17 string
		F18 string
		F19 string
		F20 string
		F21 string
		F22 string
		F23 string
		F24 string
		F25 string