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platforms/software/security/src/test/groovy/org/gradle/security/internal/SecuritySupportSpec.groovy
} keyrings[0].publicKey.userIDs[0] == "Gradle Inc. <******@****.***>" keyrings[1].publicKey.userIDs[0] == "Stian Soiland <******@****.***>" keyrings[2].publicKey.userIDs[0] == "Gradle <marc@gradle.com>" keyrings[3].publicKey.userIDs[0] == "�amonn McManus <******@****.***>" keyrings[4].publicKey.userIDs.size() == 0 } @Issue("https://github.com/gradle/gradle/issues/28400")
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Thu Mar 21 14:42:50 UTC 2024 - 2.5K bytes - Viewed (0) -
src/cmd/internal/obj/arm/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 16 15:58:33 UTC 2019 - 1.4K bytes - Viewed (0) -
src/crypto/md5/md5block_s390x.s
// http://www.zorinaq.com/papers/md5-amd64.tar.bz2 // // MD5 adapted for s390x using Go's assembler for // s390x, based on md5block_amd64.s implementation by // the Go authors. // // Author: Marc Bevand <bevand_m (at) epita.fr> // Licence: I hereby disclaim the copyright on this code and place it // in the public domain. //go:build !purego #include "textflag.h" // func block(dig *digest, p []byte)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 4.4K bytes - Viewed (0) -
src/crypto/md5/md5block_386.s
// #defines generating 8a assembly, and adjusted for 386, // by the Go Authors. //go:build !purego #include "textflag.h" // MD5 optimized for AMD64. // // Author: Marc Bevand <bevand_m (at) epita.fr> // Licence: I hereby disclaim the copyright on this code and place it // in the public domain. #define ROUND1(a, b, c, d, index, const, shift) \ XORL c, BP; \ LEAL const(a)(DI*1), a; \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 4.5K bytes - Viewed (0) -
src/crypto/md5/md5block_amd64.s
// // Translated from Perl generating GNU assembly into // #defines generating 6a assembly by the Go Authors. //go:build !purego #include "textflag.h" // MD5 optimized for AMD64. // // Author: Marc Bevand <bevand_m (at) epita.fr> // Licence: I hereby disclaim the copyright on this code and place it // in the public domain. TEXT ·block(SB),NOSPLIT,$8-32 MOVQ dig+0(FP), BP MOVQ p+8(FP), SI MOVQ p_len+16(FP), DX
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 4.8K bytes - Viewed (0) -
platforms/core-configuration/file-collections/src/integTest/groovy/org/gradle/api/file/FileCollectionIntegrationTest.groovy
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Sat Jun 08 12:54:09 UTC 2024 - 21K bytes - Viewed (0) -
src/crypto/md5/md5block_ppc64x.s
// http://www.zorinaq.com/papers/md5-amd64.tar.bz2 // // MD5 optimized for ppc64le using Go's assembler for // ppc64le, based on md5block_amd64.s implementation by // the Go authors. // // Author: Marc Bevand <bevand_m (at) epita.fr> // Licence: I hereby disclaim the copyright on this code and place it // in the public domain. //go:build (ppc64 || ppc64le) && !purego #include "textflag.h"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 20 18:05:32 UTC 2024 - 5.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/asm.go
x5 := p.getConstant(prog, op, &a[5]) // Cond is handled specially for this instruction. offset, MRC, ok := arch.ARMMRCOffset(op, cond, x0, x1, x2, x3, x4, x5) if !ok { p.errorf("unrecognized condition code .%q", cond) } prog.To.Offset = offset cond = "" prog.As = MRC // Both instructions are coded as MRC. break } if p.arch.Family == sys.PPC64 { prog.From = a[0]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 25.5K bytes - Viewed (0) -
src/cmd/internal/obj/arm/a.out.go
AREV16 AREVSH ARBIT AXTAB AXTAH AXTABU AXTAHU ABFX ABFXU ABFC ABFI AMULWT AMULWB AMULBB AMULAWT AMULAWB AMULABB AMRC // MRC/MCR ALAST // aliases AB = obj.AJMP ABL = obj.ACALL ) /* scond byte */ const ( C_SCOND = (1 << 4) - 1 C_SBIT = 1 << 4 C_PBIT = 1 << 5 C_WBIT = 1 << 6
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 05 16:22:12 UTC 2021 - 7K bytes - Viewed (0) -
src/cmd/internal/obj/arm/obj5.go
} // Replace TLS register fetches on older ARM processors. switch p.As { // Treat MRC 15, 0, <reg>, C13, C0, 3 specially. case AMRC: if p.To.Offset&0xffff0fff == 0xee1d0f70 { // Because the instruction might be rewritten to a BL which returns in R0 // the register must be zero. if p.To.Offset&0xf000 != 0 { ctxt.Diag("%v: TLS MRC instruction must write to R0 as it might get translated into a BL instruction", p.Line()) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 21.4K bytes - Viewed (0)