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Results 11 - 20 of 134 for isel (0.05 sec)
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src/cmd/asm/internal/asm/testdata/ppc64.s
CRXOR CR0GT, CR0EQ, CR0SO // 4c620982 ISEL $0, R3, R4, R5 // 7ca3201e ISEL $1, R3, R4, R5 // 7ca3205e ISEL $2, R3, R4, R5 // 7ca3209e ISEL $3, R3, R4, R5 // 7ca320de ISEL $4, R3, R4, R5 // 7ca3211e ISEL $31, R3, R4, R5 // 7ca327de ISEL CR0LT, R3, R4, R5 // 7ca3201e ISEL CR0GT, R3, R4, R5 // 7ca3205e
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
// result: (ISEL [a] x y cmp) for { x := v_0 y := v_1 if v_2.Op != OpPPC64SETBC { break } a := auxIntToInt32(v_2.AuxInt) cmp := v_2.Args[0] v.reset(OpPPC64ISEL) v.AuxInt = int32ToAuxInt(a) v.AddArg3(x, y, cmp) return true } // match: (CondSelect x y (SETBCR [a] cmp)) // result: (ISEL [a+4] x y cmp) for { x := v_0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64latelower.go
v_1 := v.Args[1] v_0 := v.Args[0] // match: (ISEL [a] x (MOVDconst [0]) z) // result: (ISELZ [a] x z) for { a := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpPPC64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } z := v_2 v.reset(OpPPC64ISELZ) v.AuxInt = int32ToAuxInt(a) v.AddArg2(x, z) return true } // match: (ISEL [a] (MOVDconst [0]) y z) // result: (ISELZ [a^0x4] y z)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 16.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
// ISEL arg2 ? arg0 : arg1 // ISELZ arg1 ? arg0 : $0 // auxInt values 0=LT 1=GT 2=EQ 3=SO (summary overflow/unordered) 4=GE 5=LE 6=NE 7=NSO (not summary overflow/not unordered) // Note, auxInt^4 inverts the comparison condition. For example, LT^4 becomes GE, and "ISEL [a] x y z" is equivalent to ISEL [a^4] y x z". {name: "ISEL", argLength: 3, reg: crgp21, asm: "ISEL", aux: "Int32", typ: "Int32"},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/doc.go
identifies a CR then the resulting condition is set in that field to be read by a later branch or isel instruction. Within these fields, bits are set to indicate less than, greater than, or equal conditions. Once an instruction sets a condition, then a subsequent branch, isel or other instruction can read the condition field and operate based on the bit settings. Examples:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 16:47:45 UTC 2023 - 11.3K bytes - Viewed (0) -
src/crypto/internal/nistec/p256_asm_ppc64le.s
LXVD2X (P2ptr+R16), X2L LXVD2X (P2ptr+R17), Y2H LXVD2X (P2ptr+R18), Y2L LXVD2X (P2ptr+R19), Z2H LXVD2X (P2ptr+R20), Z2L VSEL X1H, X2H, SEL, X1H VSEL X1L, X2L, SEL, X1L VSEL Y1H, Y2H, SEL, Y1H VSEL Y1L, Y2L, SEL, Y1L VSEL Z1H, Z2H, SEL, Z1H VSEL Z1L, Z2L, SEL, Z1L STXVD2X X1H, (P3ptr+R0) STXVD2X X1L, (P3ptr+R16) STXVD2X Y1H, (P3ptr+R17) STXVD2X Y1L, (P3ptr+R18) STXVD2X Z1H, (P3ptr+R19)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 56.5K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go
return "0" } return arg.String() case CondReg: // The CondReg can either be found in a CMP, where the // condition register field is being set, or in an instruction // like a branch or isel that is testing a bit in a condition // register field. if arg == CR0 && strings.HasPrefix(inst.Op.String(), "cmp") { return "" // don't show cr0 for cmp instructions } else if arg >= CR0 {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 12.2K bytes - Viewed (0) -
src/math/big/arith_ppc64x.s
RET zeroshift: CMP R6, $0 // x is null, nothing to copy BEQ done CMP R6, R3 // if x is same as z, nothing to copy BEQ done CMP R7, R4 ISEL $0, R7, R4, R7 // Take the lower bound of lengths of x,z SLD $3, R7, R7 SUB R6, R3, R11 // dest - src CMPU R11, R7, CR2 // < len? BLT CR2, backward // there is overlap, copy backwards
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 16.8K bytes - Viewed (0) -
src/cmd/compile/internal/ppc64/ssa.go
p.To.Type = obj.TYPE_MEM p.To.Reg = v.Args[0].Reg() case ssa.OpPPC64ISEL, ssa.OpPPC64ISELZ: // ISEL AuxInt ? arg0 : arg1 // ISELZ is a special case of ISEL where arg1 is implicitly $0. // // AuxInt value indicates conditions 0=LT 1=GT 2=EQ 3=SO 4=GE 5=LE 6=NE 7=NSO. // ISEL accepts a CR bit argument, not a condition as expressed by AuxInt.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 55.4K bytes - Viewed (0)