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Results 11 - 19 of 19 for MOVB (0.05 sec)
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src/cmd/asm/internal/asm/testdata/loong64enc2.s
MOVWU R4, name(SB) // 1e00001ac4038029 MOVV R4, name(SB) // 1e00001ac403c029 MOVB R4, name(SB) // 1e00001ac4030029 MOVBU R4, name(SB) // 1e00001ac4030029 MOVF F4, name(SB) // 1e00001ac403402b MOVD F4, name(SB) // 1e00001ac403c02b MOVW name(SB), R4 // 1e00001ac4038028 MOVWU name(SB), R4 // 1e00001ac403802a MOVV name(SB), R4 // 1e00001ac403c028 MOVB name(SB), R4 // 1e00001ac4030028 MOVBU name(SB), R4 // 1e00001ac403002a
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 27 00:46:52 UTC 2025 - 5.6K bytes - Viewed (0) -
src/cmd/asm/internal/lex/lex_test.go
"\tMOVBLZX (off*4)(R12), reg \\", "\tADDB reg, DX", "KEYROUND(X0, LOAD, 8, AX, BX, 0)", ), "\n.MOVBLZX.(.BP.).(.DX.*.4.).,.R8.\n.\n.MOVBLZX.(.(.8.+.1.).*.4.).(.R12.).,.BX.\n.ADDB.BX.,.DX.\n.MOVB.R8.,.(.8.*.4.).(.R12.).\n.PINSRW.$.0.,.(.BP.).(.R8.*.4.).,.X0.\n", }, { "taken #ifdef", lines( "#define A", "#ifdef A", "#define B 1234", "#endif", "B", ), "1234.\n",
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Tue Aug 29 07:48:38 UTC 2023 - 5.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
MOVD F4, F5 // 85981401 MOVW R4, result+16(FP) // 64608029 MOVWU R4, result+16(FP) // 64608029 MOVV R4, result+16(FP) // 6460c029 MOVB R4, result+16(FP) // 64600029 MOVBU R4, result+16(FP) // 64600029 MOVW R4, 1(R5) // a4048029 MOVWU R4, 1(R5) // a4048029 MOVV R4, 1(R5) // a404c029 MOVB R4, 1(R5) // a4040029 MOVBU R4, 1(R5) // a4040029 SC R4, 4096(R5) // a4001021 SCV R4, 4096(R5) // a4001023
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 27 00:46:52 UTC 2025 - 44.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
MOV (X5), X6 // 03b30200 MOV 4(X5), X6 // 03b34200 MOVB (X5), X6 // 03830200 MOVB 4(X5), X6 // 03834200 MOVH (X5), X6 // 03930200 MOVH 4(X5), X6 // 03934200 MOVW (X5), X6 // 03a30200 MOVW 4(X5), X6 // 03a34200 MOV X5, (X6) // 23305300 MOV X5, 4(X6) // 23325300 MOVB X5, (X6) // 23005300 MOVB X5, 4(X6) // 23025300 MOVH X5, (X6) // 23105300
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 73.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64error.s
CSRRWI $1, TIME, (X15) // ERROR "needs an integer register output" MOV $errors(SB), (X5) // ERROR "address load must target register" MOV $8(SP), (X5) // ERROR "address load must target register" MOVB $8(SP), X5 // ERROR "unsupported address load" MOVH $8(SP), X5 // ERROR "unsupported address load" MOVW $8(SP), X5 // ERROR "unsupported address load" MOVF $8(SP), X5 // ERROR "unsupported address load"
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Wed Sep 24 13:21:53 UTC 2025 - 26.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc.s
MOVB $7, (BX) // c60307 MOVB $7, (R11) // 41c60307 MOVB $7, DL // c6c207 or b207 MOVB $7, R11 // 41c6c307 or 41b307 MOVB DL, (BX) // 8813 MOVB R11, (BX) // 44881b MOVB DL, (R11) // 418813
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Fri Oct 08 21:38:44 UTC 2021 - 581.9K bytes - Viewed (1) -
src/cmd/asm/internal/asm/testdata/arm64error.s
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Tue Oct 14 19:00:00 UTC 2025 - 38.4K bytes - Viewed (0) -
lib/fips140/v1.1.0-rc1.zip
0(X11), X16 MOVBU 0(X12), X17 MOVBU 1(X11), X18 MOVBU 1(X12), X19 XOR X16, X17 XOR X18, X19 MOVB X17, 0(X10) MOVB X19, 1(X10) MOVBU 2(X11), X20 MOVBU 2(X12), X21 MOVBU 3(X11), X22 MOVBU 3(X12), X23 XOR X20, X21 XOR X22, X23 MOVB X21, 2(X10) MOVB X23, 3(X10) ADD $4, X10 ADD $4, X11 ADD $4, X12 SUB $4, X13 BGE X13, X15, loop4 PCALIGN $16 loop1: BEQZ X13, done MOVBU 0(X11), X16 MOVBU 0(X12), X17 XOR X16, X17 MOVB X17, 0(X10) ADD $1, X10 ADD $1, X11 ADD $1, X12 SUB $1, X13 JMP loop1 done: RET golang.or...
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Dec 11 16:27:41 UTC 2025 - 663K bytes - Viewed (0) -
lib/fips140/v1.0.0-c2097c7c.zip
slices PCALIGN $16 loop16b: MOVOU (SI)(AX*1), X0 // XOR 16byte forwards. MOVOU (CX)(AX*1), X1 PXOR X1, X0 MOVOU X0, (BX)(AX*1) ADDQ $16, AX CMPQ DX, AX JNE loop16b RET PCALIGN $16 loop_1b: SUBQ $1, DX // XOR 1byte backwards. MOVB (SI)(DX*1), DI MOVB (CX)(DX*1), AX XORB AX, DI MOVB DI, (BX)(DX*1) TESTQ $7, DX // AND 7 & len, if not zero jump to loop_1b. JNZ loop_1b CMPQ DX, $0 // if len is 0, ret. JE ret TESTQ $15, DX // AND 15 & len, if zero jump to aligned. JZ aligned not_aligned: TESTQ $7, DX // AND...
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Sep 25 19:53:19 UTC 2025 - 642.7K bytes - Viewed (0)