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Results 1 - 10 of 10 for SRDconst (0.16 sec)
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src/cmd/compile/internal/ssa/_gen/PPC64.rules
(MOV(BZ|B)reg (S(R|RA)Wconst [c] x)) && sizeof(x.Type) == 8 => (S(R|RA)Wconst [c] x) // initial right shift will handle sign/zero extend (MOVBZreg (SRDconst [c] x)) && c>=56 => (SRDconst [c] x) (MOVBreg (SRDconst [c] x)) && c>56 => (SRDconst [c] x) (MOVBreg (SRDconst [c] x)) && c==56 => (SRADconst [c] x) (MOVBreg (SRADconst [c] x)) && c>=56 => (SRADconst [c] x) (MOVBZreg (SRWconst [c] x)) && c>=24 => (SRWconst [c] x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390X.rules
(Div8 x y) => (DIVW (MOVBreg x) (MOVBreg y)) (Div8u x y) => (DIVWU (MOVBZreg x) (MOVBZreg y)) (Hmul(64|64u) ...) => (MULH(D|DU) ...) (Hmul32 x y) => (SRDconst [32] (MULLD (MOVWreg x) (MOVWreg y))) (Hmul32u x y) => (SRDconst [32] (MULLD (MOVWZreg x) (MOVWZreg y))) (Mod64 x y) => (MODD x y) (Mod64u ...) => (MODDU ...) // MODW/MODWU has a 64-bit dividend and a 32-bit divisor,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules
(AND x:(MOVDconst [m]) n) && m != 0 && isPPC64ValidShiftMask(^m) => (RLDICR [encodePPC64RotateMask(0,m,64)] n) // If the RLDICL does not rotate its value, a shifted value can be merged. (RLDICL [em] x:(SRDconst [s] a)) && (em&0xFF0000) == 0 => (RLDICL [mergePPC64RLDICLandSRDconst(em, s)] a) // Convert rotated 32 bit masks on 32 bit values into rlwinm. In general, this leaves the upper 32 bits in an undefined state.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 3.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64latelower.go
v.AuxInt = int32ToAuxInt(a ^ 0x4) v.AddArg2(y, z) return true } return false } func rewriteValuePPC64latelower_OpPPC64RLDICL(v *Value) bool { v_0 := v.Args[0] // match: (RLDICL [em] x:(SRDconst [s] a)) // cond: (em&0xFF0000) == 0 // result: (RLDICL [mergePPC64RLDICLandSRDconst(em, s)] a) for { em := auxIntToInt64(v.AuxInt) x := v_0 if x.Op != OpPPC64SRDconst { break }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 16.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
if !(sizeof(x.Type) == 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (MOVBZreg (SRDconst [c] x)) // cond: c>=56 // result: (SRDconst [c] x) for { if v_0.Op != OpPPC64SRDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(c >= 56) { break }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewrite.go
mb, me = men, mbn } return int64(me) | int64(mb<<8) | int64(rotate<<16) | int64(nbits<<24) } // Merge (RLDICL [encoded] (SRDconst [s] x)) into (RLDICL [new_encoded] x) // SRDconst on PPC64 is an extended mnemonic of RLDICL. If the input to an // RLDICL is an SRDconst, and the RLDICL does not rotate its value, the two // operations can be combined. This functions assumes the two opcodes can
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 64.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteS390X.go
v.AddArg3(ptr, val, mem) return true } } func rewriteValueS390X_OpAvg64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Avg64u <t> x y) // result: (ADD (SRDconst <t> (SUB <t> x y) [1]) y) for { t := v.Type x := v_0 y := v_1 v.reset(OpS390XADD) v0 := b.NewValue0(v.Pos, OpS390XSRDconst, t) v0.AuxInt = uint8ToAuxInt(1)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 395.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390XOps.go
{name: "SRW", argLength: 2, reg: sh21, asm: "SRW"}, // unsigned uint32(arg0) >> arg1, shift amount is mod 64 {name: "SRDconst", argLength: 1, reg: gp11, asm: "SRD", aux: "UInt8"}, // unsigned arg0 >> auxint, shift amount 0-63 {name: "SRWconst", argLength: 1, reg: gp11, asm: "SRW", aux: "UInt8"}, // unsigned uint32(arg0) >> auxint, shift amount 0-31
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 52.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRDconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRD, reg: regInfo{ inputs: []inputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)