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Results 1 - 10 of 11 for MOVFW (0.13 sec)
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src/cmd/asm/internal/asm/testdata/armv6.s
MOVF F4, F5 // 445ab0ee MOVD F6, F7 // 467bb0ee MOVFW F6, F8 // c68abdee MOVFW F6, R8 // c6fabdee108b1fee MOVFW.U F6, F8 // c68abcee MOVFW.U F6, R8 // c6fabcee108b1fee MOVDW F6, F8 // c68bbdee
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Dec 21 16:30:51 UTC 2017 - 4.6K bytes - Viewed (0) -
src/cmd/internal/obj/arm/anames.go
"BEQ", "BNE", "BCS", "BHS", "BCC", "BLO", "BMI", "BPL", "BVS", "BVC", "BHI", "BLS", "BGE", "BLT", "BGT", "BLE", "MOVWD", "MOVWF", "MOVDW", "MOVFW", "MOVFD", "MOVDF", "MOVF", "MOVD", "CMPF", "CMPD", "ADDF", "ADDD", "SUBF", "SUBD", "MULF", "MULD", "NMULF", "NMULD", "MULAF", "MULAD", "NMULAF", "NMULAD",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 16 15:58:33 UTC 2019 - 1.4K bytes - Viewed (0) -
src/cmd/internal/obj/mips/anames.go
"CMPGTF", "DIV", "DIVD", "DIVF", "DIVU", "DIVW", "GOK", "LL", "LLV", "LUI", "MADD", "MOVB", "MOVBU", "MOVD", "MOVDF", "MOVDW", "MOVF", "MOVFD", "MOVFW", "MOVH", "MOVHU", "MOVW", "MOVWD", "MOVWF", "MOVWL", "MOVWR", "MSUB", "MUL", "MULD", "MULF", "MULU", "MULW", "NEGD", "NEGF", "NEGW", "NEGV", "NOOP",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 1.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/armerror.s
MOVWF R1, CPSR // ERROR "illegal combination" MOVDW CPSR, R2 // ERROR "illegal combination" MOVFW CPSR, R2 // ERROR "illegal combination" MOVDW R1, CPSR // ERROR "illegal combination" MOVFW R1, CPSR // ERROR "illegal combination" BFX $12, $41, R2, R3 // ERROR "wrong width or LSB" BFX $12, $-2, R2 // ERROR "wrong width or LSB"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Nov 03 14:06:21 UTC 2017 - 14.4K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/anames.go
"BGE", "BLT", "BLTU", "BGEU", "DIV", "DIVD", "DIVF", "DIVU", "DIVW", "LL", "LLV", "LUI", "MOVB", "MOVBU", "MOVD", "MOVDF", "MOVDW", "MOVF", "MOVFD", "MOVFW", "MOVH", "MOVHU", "MOVW", "MOVWD", "MOVWF", "MOVWL", "MOVWR", "MUL", "MULD", "MULF", "MULU", "MULH", "MULHU", "MULW", "NEGD", "NEGF", "NEGW", "NEGV",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 1.9K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go
{VCVT_EQ_F32_F64, []int{1, 0}, "VCVT", "MOVDF"}, {VCVT_EQ_F32_U32, []int{1, 0}, "VCVT", "MOVWF.U"}, {VCVT_EQ_F32_S32, []int{1, 0}, "VCVT", "MOVWF"}, {VCVT_EQ_S32_F32, []int{1, 0}, "VCVT", "MOVFW"}, {VCVT_EQ_U32_F32, []int{1, 0}, "VCVT", "MOVFW.U"}, {VCVT_EQ_F64_U32, []int{1, 0}, "VCVT", "MOVWD.U"}, {VCVT_EQ_F64_S32, []int{1, 0}, "VCVT", "MOVWD"}, {VCVT_EQ_S32_F64, []int{1, 0}, "VCVT", "MOVDW"},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 11.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
SRLV $32, R4 // 84804500 MASKEQZ R4, R5, R6 // a6101300 MASKNEZ R4, R5, R6 // a6901300 MOVFD F4, F5 // 85241901 MOVDF F4, F5 // 85181901 MOVWF F4, F5 // 85101d01 MOVFW F4, F5 // 85041b01 MOVWD F4, F5 // 85201d01 MOVDW F4, F5 // 85081b01 NEGF F4, F5 // 85141401 NEGD F4, F5 // 85181401 ABSD F4, F5 // 85081401 TRUNCDW F4, F5 // 85881a01
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 8.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
{name: "MOVWUD", argLength: 1, reg: gpfp, asm: "MOVWD"}, // uint32 -> float64, set U bit in the instruction {name: "MOVFW", argLength: 1, reg: fpgp, asm: "MOVFW"}, // float32 -> int32 {name: "MOVDW", argLength: 1, reg: fpgp, asm: "MOVDW"}, // float64 -> int32 {name: "MOVFWU", argLength: 1, reg: fpgp, asm: "MOVFW"}, // float32 -> uint32, set U bit in the instruction
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0) -
src/cmd/internal/obj/arm/asm5.go
o1 |= (uint32(p.From.Reg) & 15) << 0 o1 |= (uint32(p.To.Reg) & 15) << 12 // macro for movfw freg,FTMP; movw FTMP,reg case 86: /* movfw freg,reg - truncate float-to-fix */ o1 = c.oprrr(p, p.As, int(p.Scond)) o1 |= (uint32(p.From.Reg) & 15) << 0 o1 |= (FREGTMP & 15) << 12 o2 = c.oprrr(p, -AMOVFW, int(p.Scond)) o2 |= (FREGTMP & 15) << 16
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 79.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM.rules
// float <-> int conversion (Cvt32to32F ...) => (MOVWF ...) (Cvt32to64F ...) => (MOVWD ...) (Cvt32Uto32F ...) => (MOVWUF ...) (Cvt32Uto64F ...) => (MOVWUD ...) (Cvt32Fto32 ...) => (MOVFW ...) (Cvt64Fto32 ...) => (MOVDW ...) (Cvt32Fto32U ...) => (MOVFWU ...) (Cvt64Fto32U ...) => (MOVDWU ...) (Cvt32Fto64F ...) => (MOVFD ...) (Cvt64Fto32F ...) => (MOVDF ...) (Round(32|64)F ...) => (Copy ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0)