- Sort Score
- Result 10 results
- Languages All
Results 1 - 10 of 11 for mfvscr (0.11 sec)
-
src/cmd/internal/obj/ppc64/anames.go
"LXVX", "LXVDSX", "STXV", "STXVL", "STXVLL", "STXVD2X", "STXVW4X", "STXVH8X", "STXVB16X", "STXVX", "LXSDX", "STXSDX", "LXSIWAX", "LXSIWZX", "STXSIWX", "MFVSRD", "MFFPRD", "MFVRD", "MFVSRWZ", "MFVSRLD", "MTVSRD", "MTFPRD", "MTVRD", "MTVSRWA", "MTVSRWZ", "MTVSRDD", "MTVSRWS", "XXLAND", "XXLANDC", "XXLEQV",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
test/codegen/math.go
func fnma(x, y, z float64) float64 { // riscv64:"FNMADDD",-"FNMSUBD" return math.FMA(x, -y, -z) } func fromFloat64(f64 float64) uint64 { // amd64:"MOVQ\tX.*, [^X].*" // arm64:"FMOVD\tF.*, R.*" // ppc64x:"MFVSRD" // mips64/hardfloat:"MOVV\tF.*, R.*" return math.Float64bits(f64+1) + 1 } func fromFloat32(f32 float32) uint32 { // amd64:"MOVL\tX.*, [^X].*" // arm64:"FMOVS\tF.*, R.*"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 04 15:24:29 UTC 2024 - 6.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
// Lowering float <=> int (Cvt32to(32|64)F x) => ((FCFIDS|FCFID) (MTVSRD (SignExt32to64 x))) (Cvt64to(32|64)F x) => ((FCFIDS|FCFID) (MTVSRD x)) (Cvt32Fto(32|64) x) => (MFVSRD (FCTI(W|D)Z x)) (Cvt64Fto(32|64) x) => (MFVSRD (FCTI(W|D)Z x)) (Cvt32Fto64F ...) => (Copy ...) // Note v will have the wrong type for patterns dependent on Float32/Float64 (Cvt64Fto32F ...) => (FRSP ...) (CvtBoolToUint8 ...) => (Copy ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9.go
v = c.regoff(p.GetFrom3()) & 255 } else { v = 255 } o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11 case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */ if p.To.Reg == 0 { c.ctxt.Diag("must specify FPSCR(n)\n%v", p) } o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12 case 66: /* mov spr,r1; mov r1,spr */ var r int var v int32
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0) -
src/hash/crc32/crc32_ppc64le.s
VSLDOI $8,V0,zeroes,V0 #else VAND V0,mask_32bit,V1 VPMSUMD V1,const1,V1 VAND V1,mask_32bit,V1 VPMSUMD V1,const2,V1 VXOR V0,V1,V0 VSLDOI $4,V0,zeroes,V0 #endif MFVSRD VS32,R3 // VS32 = V0 NOR R3,R3,R3 // return ^crc MOVW R3,ret+32(FP) RET first_warm_up_done: LVX (R3),const1 ADD $16,R3 VPMSUMD V16,const1,V8 VPMSUMD V17,const1,V9
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 06 12:09:50 UTC 2024 - 13.1K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/a.out.go
C_SOREG /* An $n+reg memory arg where n is a 16 bit signed offset */ C_LOREG /* An $n+reg memory arg where n is a 32 bit signed offset */ C_XOREG /* An reg+reg memory arg */ C_FPSCR /* The fpscr register */ C_LR /* The link register */ C_CTR /* The count register */ C_ANY /* Any argument */ C_GOK /* A non-matched argument */ C_ADDR /* A symbolic memory location */
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
// There are optimizations that should apply -- (Xi2f64 (MOVWload (not-ADD-ptr+offset) ) ) could use // the word-load instructions. (Xi2f64 (MOVDload ptr )) can be (FMOVDload ptr) {name: "MFVSRD", argLength: 1, reg: fpgp, asm: "MFVSRD", typ: "Int64"}, // move 64 bits of F register into G register {name: "MTVSRD", argLength: 1, reg: gpfp, asm: "MTVSRD", typ: "Float64"}, // move 64 bits of G register into F register
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/runtime/asm_arm.s
// disable runfast (flush-to-zero) mode of vfp if runtime.goarmsoftfp == 0 MOVB runtime·goarmsoftfp(SB), R11 CMP $0, R11 BNE 4(PC) WORD $0xeef1ba10 // vmrs r11, fpscr BIC $(1<<24), R11 WORD $0xeee1ba10 // vmsr fpscr, r11 RET TEXT runtime·mstart(SB),NOSPLIT|TOPFRAME,$0 BL runtime·mstart0(SB) RET // not reached /* * go-routine */ // void gogo(Gobuf*)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 23 21:00:52 UTC 2024 - 32.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
LXSIWZX (R3), VS1 // 7c201818 STXSIWX VS1, (R3)(R4) // 7c241918 STXSIWX VS1, (R3)(R0) // 7c201918 STXSIWX VS1, (R3) // 7c201918 MFVSRD VS1, R3 // 7c230066 MTFPRD R3, F0 // 7c030166 MFVRD V0, R3 // 7c030067 MFVSRLD VS63,R4 // 7fe40267 MFVSRLD V31,R4 // 7fe40267
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
b := v.Block typ := &b.Func.Config.Types // match: (MFVSRD (FMOVDconst [c])) // result: (MOVDconst [int64(math.Float64bits(c))]) for { if v_0.Op != OpPPC64FMOVDconst { break } c := auxIntToFloat64(v_0.AuxInt) v.reset(OpPPC64MOVDconst) v.AuxInt = int64ToAuxInt(int64(math.Float64bits(c))) return true } // match: (MFVSRD x:(FMOVDload [off] {sym} ptr mem))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0)