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Results 1 - 10 of 14 for sbc (0.03 sec)
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src/cmd/asm/internal/asm/testdata/arm.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
src/runtime/time_windows_arm.s
DMB MB_ISH MOVW time_hi2(R3), R2 CMP R1, R2 BNE wall // w = R1:R0 in 100ns untis // convert to Unix epoch (but still 100ns units) #define delta 116444736000000000 SUB.S $(delta & 0xFFFFFFFF), R0 SBC $(delta >> 32), R1 // Convert to nSec MOVW $100, R2 MULLU R0, R2, (R4, R3) // R4:R3 = R1:R0 * R2 MULA R1, R2, R4, R4 // w = R2:R1 in nSec MOVW R3, R1 // R4:R3 -> R2:R1 MOVW R4, R2
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Sep 07 17:19:45 UTC 2023 - 2K bytes - Viewed (0) -
src/math/big/arith_arm.s
RET // func subVV(z, x, y []Word) (c Word) // (same as addVV except for SBC instead of ADC and label names) TEXT ·subVV(SB),NOSPLIT,$0 SUB.S $0, R0 // clear borrow flag MOVW z+0(FP), R1 MOVW z_len+4(FP), R4 MOVW x+12(FP), R2 MOVW y+24(FP), R3 ADD R4<<2, R1, R4 B E2 L2: MOVW.P 4(R2), R5 MOVW.P 4(R3), R6 SBC.S R6, R5 MOVW.P R5, 4(R1) E2: TEQ R1, R4 BNE L2 MOVW $0, R0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 4K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 18 01:40:37 UTC 2023 - 5.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
{name: "RSBSconst", argLength: 1, reg: gp11carry, asm: "RSB", aux: "Int32"}, // auxInt - arg0, set carry flag {name: "SBC", argLength: 3, reg: gp2flags1, asm: "SBC"}, // arg0 - arg1 - carry, arg2=flags {name: "SBCconst", argLength: 2, reg: gp1flags1, asm: "SBC", aux: "Int32"}, // arg0 - auxInt - carry, arg1=flags
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM.rules
(SUB (SRA y z) x) => (RSBshiftRAreg x y z) (SBC x (SLLconst [c] y) flags) => (SBCshiftLL x y [c] flags) (SBC (SLLconst [c] y) x flags) => (RSCshiftLL x y [c] flags) (SBC x (SRLconst [c] y) flags) => (SBCshiftRL x y [c] flags) (SBC (SRLconst [c] y) x flags) => (RSCshiftRL x y [c] flags) (SBC x (SRAconst [c] y) flags) => (SBCshiftRA x y [c] flags) (SBC (SRAconst [c] y) x flags) => (RSCshiftRA x y [c] flags) (SBC x (SLL y z) flags) => (SBCshiftLLreg x y z flags)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0) -
src/crypto/internal/nistec/p256_asm_arm64.s
MOVD $0, acc2 MOVD p256const1<>(SB), acc3 // Load the original value LDP 0*16(a_ptr), (t0, t1) LDP 1*16(a_ptr), (t2, t3) // Speculatively subtract SUBS t0, acc0 SBCS t1, acc1 SBCS t2, acc2 SBC t3, acc3 // If condition is 0, keep original value CMP $0, hlp0 CSEL EQ, t0, acc0, acc0 CSEL EQ, t1, acc1, acc1 CSEL EQ, t2, acc2, acc2 CSEL EQ, t3, acc3, acc3 // Store result
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 29.7K bytes - Viewed (0) -
src/cmd/internal/obj/arm/asm5.go
as2 = p.As // ADD, SUB, ORR, EOR, BIC case ARSB: as2 = AADD // RSB -> RSB/ADD pair case AADC: as2 = AADD // ADC -> ADC/ADD pair case ASBC: as2 = ASUB // SBC -> SBC/SUB pair case ARSC: as2 = AADD // RSC -> RSC/ADD pair default: c.ctxt.Diag("unknown second op for %v", p) } o1 = c.oprrr(p, p.As, int(p.Scond)) o2 = c.oprrr(p, as2, int(p.Scond))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 79.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
RORW $28, R14, R15 // cf718e13 RORW R3, R12, R3 // 832dc31a ROR R0, R23, R2 // e22ec09a SBCW R4, R8, R24 // 1801045a SBC R25, R10, R26 // 5a0119da SBCSW R27, R19, R19 // 73021b7a SBCS R5, R9, R5 // 250105fa SBFIZW $9, R10, $18, R22 // 56451713
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM.go
v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBC (MOVWconst [c]) x flags) // result: (RSCconst [c] x flags) for { if v_0.Op != OpARMMOVWconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 flags := v_2 v.reset(OpARMRSCconst) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, flags) return true } // match: (SBC x (MOVWconst [c]) flags)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 486.8K bytes - Viewed (0)