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Results 1 - 10 of 71 for fsub (0.06 sec)
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src/math/modf_ppc64x.s
//go:build ppc64 || ppc64le #include "textflag.h" // func archModf(f float64) (int float64, frac float64) TEXT ·archModf(SB),NOSPLIT,$0 FMOVD f+0(FP), F0 FRIZ F0, F1 FMOVD F1, int+8(FP) FSUB F1, F0, F2 FCPSGN F2, F0, F2 FMOVD F2, frac+16(FP)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 416 bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/x86/x86asm/gnu.go
switch inst.Op { case FDIV: inst.Op = FDIVR case FDIVR: inst.Op = FDIV case FSUB: inst.Op = FSUBR case FSUBR: inst.Op = FSUB case FDIVP: inst.Op = FDIVRP case FDIVRP: inst.Op = FDIVP case FSUBP: inst.Op = FSUBRP case FSUBRP: inst.Op = FSUBP } } case MOVNTSD: // MOVNTSD is F2 0F 2B /r.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 21.4K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/anames.go
"FMOVSU", "FMOVSX", "FMOVSZ", "FMSUB", "FMSUBCC", "FMSUBS", "FMSUBSCC", "FMUL", "FMULCC", "FMULS", "FMULSCC", "FNABS", "FNABSCC", "FNEG", "FNEGCC", "FNMADD", "FNMADDCC", "FNMADDS", "FNMADDSCC", "FNMSUB", "FNMSUBCC", "FNMSUBS", "FNMSUBSCC", "FRSP", "FRSPCC", "FSUB", "FSUBCC", "FSUBS", "FSUBSCC", "ISEL", "MOVMW",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 7.1K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
case DIVD, DIVDCC, DIVDU, DIVDUCC, DIVDE, DIVDECC, DIVDEU, DIVDEUCC, DIVDO, DIVDOCC, DIVDUO, DIVDUOCC: return true case MODUD, MODSD, MODUW, MODSW: return true case FADD, FADDS, FSUB, FSUBS, FMUL, FMULS, FDIV, FDIVS, FMADD, FMADDS, FMSUB, FMSUBS, FNMADD, FNMADDS, FNMSUB, FNMSUBS, FMULSCC: return true case FADDCC, FADDSCC, FSUBCC, FMULCC, FDIVCC, FDIVSCC: return true
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 10.9K bytes - Viewed (0) -
src/math/pow_s390x.s
MOVW R1, R6 CMPBEQ R6, $0, L29 LTDBR F2, F2 BLTU L50 FMOVD F2, F4 L14: MOVD $·pow_x433<>+0(SB), R1 FMOVD 0(R1), F7 WFCHDBS V4, V7, V3 BEQ L15 WFADB V7, V4, V3 FSUB F7, F3 WFCEDBS V4, V3, V3 BEQ L15 LTDBR F0, F0 FMOVD 8(R9), F4 BNE L16 L13: LTDBR F2, F2 BLT L18 L40: FMOVD $0, F0 WFMDB V4, V0, V1 BR L1 L49: WFMDB V0, V4, V1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jun 14 00:03:57 UTC 2023 - 16.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
(F(MADD|NMADD|MSUB|NMSUB)S neg:(FNEGS x) y z) && neg.Uses == 1 => (F(NMSUB|MSUB|NMADD|MADD)S x y z) (F(MADD|NMADD|MSUB|NMSUB)S x y neg:(FNEGS z)) && neg.Uses == 1 => (F(MSUB|NMSUB|MADD|NMADD)S x y z) (F(MADD|NMADD|MSUB|NMSUB)D neg:(FNEGD x) y z) && neg.Uses == 1 => (F(NMSUB|MSUB|NMADD|MADD)D x y z)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
ADDW R1, R2, R3 // b9f81032 ADDW $8192, R1 // a71a2000 ADDW $8192, R1, R2 // ec21200000d8 ADDE R1, R2 // b9880021 SUB R3, R4 // b9090043 SUB R3, R4, R5 // b9e93054 SUB $8192, R3 // a73be000 SUB $8192, R3, R4 // ec43e00000d9 SUBC R1, R2 // b90b0021 SUBC $1, R1, R2 // ec21ffff00db SUBC R2, R3, R4 // b9eb2043
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 22 03:55:32 UTC 2023 - 21.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
FADDS F1, F2, F3 // ec62082a FADDSCC F1, F2, F3 // ec62082b FSUB F1, F2 // fc420828 FSUB F1, F2, F3 // fc620828 FSUBCC F1, F2, F3 // fc620829 FSUBS F1, F2 // ec420828 FSUBS F1, F2, F3 // ec620828 FSUBCC F1, F2, F3 // fc620829 FSUBSCC F1, F2, F3 // ec620829
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0)