(MOVBUreg (ANDI [c] x)) && c < 0 => (ANDI [int64(uint8(c))] x)
(MOVHUreg (ANDI [c] x)) && c < 0 => (ANDI [int64(uint16(c))] x)
(MOVWUreg (ANDI [c] x)) && c < 0 => (AND (MOVDconst [int64(uint32(c))]) x)

// Avoid sign/zero extension for consts.
(MOVBreg  (MOVDconst [c])) => (MOVDconst [int64(int8(c))])
(MOVHreg  (MOVDconst [c])) => (MOVDconst [int64(int16(c))])
(MOVWreg  (MOVDconst [c])) => (MOVDconst [int64(int32(c))])

	MULHDU	R5, R14, R11	// high x[i]*y
	ADDC	R15, R10
	ADDZE	R11
	ADDC	R9, R10
	ADDZE	R11, R9
	MULLD	R5, R16, R14	// low x[i+1]*y
	MULHDU	R5, R16, R15	// high x[i+1]*y
	ADDC	R17, R14
	ADDZE	R15
	ADDC	R9, R14
	ADDZE	R15, R9
	MULLD	R5, R18, R16	// low x[i+2]*y
	MULHDU	R5, R18, R17	// high x[i+2]*y
	ADDC	R19, R16
	ADDZE	R17
	ADDC	R9, R16
	ADDZE	R17, R9
	MULLD	R5, R20, R18	// low x[i+3]*y

	ADDC   h0, t1, t1;  \
	MULLD  h2, r1, t3;  \
	ADDZE  t4, h0;      \
	MULHDU r1, h1, t5;  \
	MULLD  r1, h1, t4;  \
	ADDC   t4, t2, t2;  \
	ADDE   t5, t3, t3;  \
	ADDC   h0, t2, t2;  \
	MOVD   $-4, t4;     \
	ADDZE  t3;          \
	RLDICL $0, t2, $62, h2; \
	AND    t2, t4, h0;  \
	ADDC   t0, h0, h0;  \
	ADDE   t3, t1, h1;  \
	SLD    $62, t3, t4; \
	SRD    $2, t2;      \
	ADDZE  h2;          \

		{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},                           // arg0&arg1
		{name: "ANDN", argLength: 2, reg: gp21, asm: "ANDN"},                                            // arg0&^arg1
		{name: "ANDNCC", argLength: 2, reg: gp21, asm: "ANDNCC", typ: "(Int64,Flags)"},                  // arg0&^arg1 sets CC

package lifecycle

import (
	"encoding/xml"
)

var errDuplicateTagKey = Errorf("Duplicate Tag Keys are not allowed")

// And - a tag to combine a prefix and multiple tags for lifecycle configuration rule.
type And struct {
	XMLName               xml.Name `xml:"And"`
	ObjectSizeGreaterThan int64    `xml:"ObjectSizeGreaterThan,omitempty"`
	ObjectSizeLessThan    int64    `xml:"ObjectSizeLessThan,omitempty"`

	RORL	$2, DI; \
	MOVL	a, DX; \
	ANDL	b, BX; \
	RORL	$13, DX; \
	MOVL	a, CX; \
	ANDL	c, CX; \
	XORL	DX, DI; \
	XORL	CX, BX; \
	MOVL	a, DX; \
	MOVL	b, CX; \
	RORL	$22, DX; \
	ANDL	a, CX; \
	XORL	CX, BX; \
	XORL	DX, DI; \
	ADDL	DI, BX

// Calculate T1 and T2, then e = d + T1 and a = T1 + T2.
// The values for e and a are stored in d and h, ready for rotation.

	MOVD R0, c+56(FP)
	RET

// Update position of x(R6) and z(R8) based on the current counter value and perform copying.
// With the assumption that x and z will not overlap with each other or x and z will
// point to same memory region, we can use a faster version of copy using only MVC here.
// In the following implementation, we have three copy loops, each copying a word, 4 words, and

func set16(x8 int8, u8 *uint8, y8 int8, z8 uint8) {
	// Truncate not needed, load does sign/zero extend

	// ppc64x:-"MOVBZ\tR\\d+,\\sR\\d+"
	val16[0] = uint16(*u8)

	// AND not needed due to size
	// ppc64x:-"ANDCC"
	sval16[1] = 255 & int16(x8+y8)

	// ppc64x:-"ANDCC"
	val16[1] = 255 & uint16(*u8+z8)

}
func shiftidx(u8 *uint8, x16 *int16, u16 *uint16) {

	// ppc64x:-"MOVBZ\tR\\d+,\\sR\\d+"
	val16[0] = uint16(sval16[*u8>>2])

	RORL	$2, AX; \
	MOVL	(a*4)(DI), DX; \
	ANDL	(b*4)(DI), BX; \
	RORL	$13, DX; \
	MOVL	(a*4)(DI), CX; \
	ANDL	(c*4)(DI), CX; \
	XORL	DX, AX; \
	XORL	CX, BX; \
	MOVL	(a*4)(DI), DX; \
	MOVL	(b*4)(DI), CX; \
	RORL	$22, DX; \
	ANDL	(a*4)(DI), CX; \
	XORL	CX, BX; \
	XORL	DX, AX; \
	ADDL	AX, BX

// Calculate T1 and T2, then e = d + T1 and a = T1 + T2.

	VADDUDM	V2, V5, V5	// The count will be fixed up afterwards.
	ADD	$32, R3
	BDNZ	cmploop

	VADDUDM	V4, V5, V5
	MFVSRD	V5, R18
	VSLDOI	$8, V5, V5, V5
	MFVSRD	V5, R21
	ADD	R21, R18, R18
	ANDCC	$31, R4, R4
	// Skip the tail processing if no bytes remaining.
	BEQ	tail_0

#ifdef GOPPC64_power10
	SRD	$3, R18, R18	// Fix the vector loop count before counting the tail on P10.

tail:	// Count the last 0 - 31 bytes.