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Results 1 - 10 of 185 for andc (0.21 sec)
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src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 10.9K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
[6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, {AND, 0xfc0007ff00000000, 0x7c00003800000000, 0x0, // AND X-form (and RA,RS,RB) [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, {ANDCC, 0xfc0007ff00000000, 0x7c00003900000000, 0x0, // AND X-form (and. RA,RS,RB) [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, {ANDC, 0xfc0007ff00000000, 0x7c00007800000000, 0x0, // AND with Complement X-form (andc RA,RS,RB)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 334.7K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_386.s
LOCK ORL BX, (AX) RET // func And(addr *uint32, v uint32) TEXT ·And(SB), NOSPLIT, $0-8 MOVL ptr+0(FP), AX MOVL val+4(FP), BX LOCK ANDL BX, (AX) RET // func And32(addr *uint32, v uint32) old uint32 TEXT ·And32(SB), NOSPLIT, $0-12 MOVL ptr+0(FP), BX MOVL val+4(FP), CX casloop: MOVL CX, DX MOVL (BX), AX ANDL AX, DX LOCK CMPXCHGL DX, (BX) JNZ casloop
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 6.5K bytes - Viewed (0) -
test/codegen/bool.go
b := !(x >= y) return b } func TestLogicalCompareZero(x *[64]uint64) { // ppc64x:"ANDCC",^"AND" b := x[0]&3 if b!=0 { x[0] = b } // ppc64x:"ANDCC",^"AND" b = x[1]&x[2] if b!=0 { x[1] = b } // ppc64x:"ANDNCC",^"ANDN" b = x[1]&^x[2] if b!=0 { x[1] = b } // ppc64x:"ORCC",^"OR" b = x[3]|x[4] if b!=0 { x[3] = b }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 13 22:12:32 UTC 2023 - 6.7K bytes - Viewed (0) -
test/codegen/bits.go
return b&0x80 == 0x80 } // Check AND masking on arm64 (Issue #19857) func and_mask_1(a uint64) uint64 { // arm64:`AND\t` return a & ((1 << 63) - 1) } func and_mask_2(a uint64) uint64 { // arm64:`AND\t` return a & (1 << 63) } func and_mask_3(a, b uint32) (uint32, uint32) { // arm/7:`BIC`,-`AND` a &= 0xffffaaaa // arm/7:`BFC`,-`AND`,-`BIC` b &= 0xffc003ff return a, b }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 7.8K bytes - Viewed (0) -
test/codegen/mathbits.go
// s390x:"ADDE","ADDC\t[$]-1," // mips64:"ADDV","SGTU" // riscv64: "ADD","SLTU" return bits.Add(x, 7, ci) } func AddZ(x, y uint) (r, co uint) { // arm64:"ADDS","ADC",-"ADCS",-"ADD\t",-"CMP" // amd64:"ADDQ","SBBQ","NEGQ",-"NEGL",-"ADCQ" // loong64: "ADDV", "SGTU" // ppc64x: "ADDC", -"ADDE", "ADDZE" // s390x:"ADDC",-"ADDC\t[$]-1," // mips64:"ADDV","SGTU" // riscv64: "ADD","SLTU"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 18:51:17 UTC 2024 - 19.6K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_amd64.s
LOCK ORB BX, (AX) RET // void ·And8(byte volatile*, byte); TEXT ·And8(SB), NOSPLIT, $0-9 MOVQ ptr+0(FP), AX MOVB val+8(FP), BX LOCK ANDB BX, (AX) RET // func Or(addr *uint32, v uint32) TEXT ·Or(SB), NOSPLIT, $0-12 MOVQ ptr+0(FP), AX MOVL val+8(FP), BX LOCK ORL BX, (AX) RET // func And(addr *uint32, v uint32) TEXT ·And(SB), NOSPLIT, $0-12 MOVQ ptr+0(FP), AX
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 5.2K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/anames.go
obj.A_ARCHSPECIFIC: "ADD", "ADDCC", "ADDIS", "ADDV", "ADDVCC", "ADDC", "ADDCCC", "ADDCV", "ADDCVCC", "ADDME", "ADDMECC", "ADDMEVCC", "ADDMEV", "ADDE", "ADDECC", "ADDEVCC", "ADDEV", "ADDZE", "ADDZECC", "ADDZEVCC", "ADDZEV", "ADDEX", "AND", "ANDCC", "ANDN", "ANDNCC", "ANDISCC", "BC", "BCL", "BEQ", "BGE", "BGT", "BLE",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
test/codegen/comparisons.go
func CmpToZero(a, b, d int32, e, f int64, deOptC0, deOptC1 bool) int32 { // arm:`TST`,-`AND` // arm64:`TSTW`,-`AND` // 386:`TESTL`,-`ANDL` // amd64:`TESTL`,-`ANDL` c0 := a&b < 0 // arm:`CMN`,-`ADD` // arm64:`CMNW`,-`ADD` c1 := a+b < 0 // arm:`TEQ`,-`XOR` c2 := a^b < 0 // arm64:`TST`,-`AND` // amd64:`TESTQ`,-`ANDQ` c3 := e&f < 0 // arm64:`CMN`,-`ADD` c4 := e+f < 0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 19 16:31:02 UTC 2024 - 15.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/generic.rules
// Ands clear bits. Ors set bits. // If a subsequent Or will set all the bits // that an And cleared, we can skip the And. // This happens in bitmasking code like: // x &^= 3 << shift // clear two old bits // x |= v << shift // set two new bits // when shift is a small constant and v ends up a constant 3.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 16 22:21:05 UTC 2024 - 135.3K bytes - Viewed (0)