"CMOVWLS",
	"CMOVWLT",
	"CMOVWMI",
	"CMOVWNE",
	"CMOVWOC",
	"CMOVWOS",
	"CMOVWPC",
	"CMOVWPL",
	"CMOVWPS",
	"CMPB",
	"CMPL",
	"CMPPD",
	"CMPPS",
	"CMPQ",
	"CMPSB",
	"CMPSD",
	"CMPSL",
	"CMPSQ",
	"CMPSS",
	"CMPSW",
	"CMPW",
	"CMPXCHG16B",
	"CMPXCHG8B",
	"CMPXCHGB",
	"CMPXCHGL",
	"CMPXCHGQ",
	"CMPXCHGW",
	"COMISD",
	"COMISS",
	"CPUID",

#ifdef NEEDS_ESPERM
	MOVD	$·rcon(SB), R11
	LVX	(R11), ESPERM   // Permute value for P8_ macros.
#endif

	// Assume len > 0 && len % blockSize == 0.
	CMPW	ENC, $0
	P8_LXVB16X(IVP, R0, IVEC)
	CMPU	ROUNDS, $10, CR1
	CMPU	ROUNDS, $12, CR2 // Only sizes 10/12/14 are supported.

	// Setup key in VSRs, and set loop count in CTR.
	LOAD_KEY(KEYP)
	SRD	$4, LEN
	MOVD	LEN, CTR

	BEQ	Lcbc_dec

		{name: "CMP", argLength: 2, reg: gp2cr, asm: "CMP", typ: "Flags"},     // arg0 compare to arg1
		{name: "CMPU", argLength: 2, reg: gp2cr, asm: "CMPU", typ: "Flags"},   // arg0 compare to arg1
		{name: "CMPW", argLength: 2, reg: gp2cr, asm: "CMPW", typ: "Flags"},   // arg0 compare to arg1
		{name: "CMPWU", argLength: 2, reg: gp2cr, asm: "CMPWU", typ: "Flags"}, // arg0 compare to arg1

}
func rewriteValueARM64latelower_OpARM64CMPWconst(v *Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (CMPWconst [c] x)
	// cond: !isARM64addcon(int64(c))
	// result: (CMPW x (MOVDconst [int64(c)]))
	for {
		c := auxIntToInt32(v.AuxInt)
		x := v_0
		if !(!isARM64addcon(int64(c))) {
			break
		}
		v.reset(OpARM64CMPW)
		v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)

	MOVD	x+0(FP), R1
	MOVD	$Neg2p11, R2
	CMPUBGT	R1, R2, usego

	FMOVD	x+0(FP), F0
	MOVD	$·erfcrodataL38<>+0(SB), R9
	FMOVD	F0, F2
	SRAD	$48, R1
	MOVH	R1, R2
	ANDW	$0x7FFF, R1
	MOVH	$Pos15, R3
	CMPW	R1, R3
	BGT	usego
	MOVH	$0x3FFF, R3
	MOVW	R1, R6
	MOVW	R3, R7
	CMPBGT	R6, R7, L2
	MOVH	$0x3FEF, R3
	MOVW	R3, R7
	CMPBGT	R6, R7, L3
	MOVH	$0x2FFF, R2
	MOVW	R2, R7
	CMPBGT	R6, R7, L4

	CMN R6, R3                                 // 7f0006ab
	CMNW R30, R5                               // bf001e2b
	CMNW $2, R5                                // bf080031
	CMN ZR, R3                                 // 7f001fab
	CMN R0, R3                                 // 7f0000ab
	CMPW R6.UXTB, R23                          // ff02266b
	CMP R25.SXTH<<2, R26                       // 5fab39eb
	CMP $3817, R29                             // bfa73bf1

	MOVD	R12, -24(R1)
	MOVD	$1234, R10
	MOVD	R10, -32(R1)

	MOVD	$SYS_clone, R8
	SVC

	// In parent, return.
	CMP	ZR, R0
	BEQ	child
	MOVW	R0, ret+40(FP)
	RET
child:

	// In child, on new stack.
	MOVD	-32(RSP), R10
	MOVD	$1234, R0
	CMP	R0, R10
	BEQ	good
	MOVD	$0, R0
	MOVD	R0, (R0)	// crash

good:
	// Initialize m->procid to Linux tid
	MOVD	$SYS_gettid, R8

	SUBSW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	CMP	R7@>2, R5                                        // ERROR "unsupported shift operator"
	CMPW	R7@>2, R5                                        // ERROR "unsupported shift operator"
	CMN	R7@>2, R5                                        // ERROR "unsupported shift operator"
	CMNW	R7@>2, R5                                        // ERROR "unsupported shift operator"

				prog.To = a[2]
			}
		case sys.I386:
			prog.From = a[0]
			prog.AddRestSource(a[1])
			prog.To = a[2]
		case sys.PPC64:
			if arch.IsPPC64CMP(op) {
				// CMPW etc.; third argument is a CR register that goes into prog.Reg.
				prog.From = a[0]
				prog.Reg = p.getRegister(prog, op, &a[2])
				prog.To = a[1]
				break
			}

			prog.From = a[0]
			prog.To = a[2]

	{VSQRT_EQ_F32, []int{1, 0}, "VSQRT", "SQRTF"},
	{VSQRT_EQ_F64, []int{1, 0}, "VSQRT", "SQRTD"},
	{VCMP_EQ_F32, []int{1, 0}, "VCMP", "CMPF"},
	{VCMP_EQ_F64, []int{1, 0}, "VCMP", "CMPD"},
	{VCMP_E_EQ_F32, []int{1, 0}, "VCMP.E", "CMPF"},
	{VCMP_E_EQ_F64, []int{1, 0}, "VCMP.E", "CMPD"},
	{VLDR_EQ, []int{1}, "VLDR", "MOV"},
	{VSTR_EQ, []int{1}, "VSTR", "MOV"},
	{VMOV_EQ_F32, []int{1, 0}, "VMOV", "MOVF"},