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Results 1 - 6 of 6 for swift (0.2 sec)

  1. src/cmd/asm/internal/asm/testdata/armerror.s

    	MOVB	R0>>8, R2          // ERROR "illegal shift"
    	MOVH	R0<<16, R2         // ERROR "illegal shift"
    	MOVBS	R0->8, R2          // ERROR "illegal shift"
    	MOVHS	R0<<24, R2         // ERROR "illegal shift"
    	MOVBU	R0->24, R2         // ERROR "illegal shift"
    	MOVHU	R0@>1, R2          // ERROR "illegal shift"
    	XTAB	R0>>8, R2          // ERROR "illegal shift"
    	XTAH	R0<<16, R2         // ERROR "illegal shift"
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Nov 03 14:06:21 GMT 2017
    - 14.4K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/arm64error.s

    	ADDS	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	ADDSW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	SUB	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	SUBW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Dec 08 03:28:17 GMT 2023
    - 37.8K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/mips.s

    	MOVW	R1, M1
    
    	//	LMOVW mreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	MOVW	M1, R1
    	MOVW	M1, R1
    
    
    	//
    	// integer operations
    	// logical instructions
    	// shift instructions
    	// unary instructions
    	//
    	//	LADDW rreg ',' sreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, int($4), &$6);
    	//	}
    	ADD	R1, R2, R3
    
    	//	LADDW imm ',' sreg ',' rreg
    	//	{
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Aug 08 12:17:12 GMT 2023
    - 6.7K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/mips64.s

    //	LMOVW mreg ',' rreg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	MOVW	M1, R1 // 40010800
    	MOVV	M1, R1 // 40210800
    
    
    //
    // integer operations
    // logical instructions
    // shift instructions
    // unary instructions
    //
    //	LADDW rreg ',' sreg ',' rreg
    //	{
    //		outcode(int($1), &$2, int($4), &$6);
    //	}
    	ADD	R5, R9, R10	// 01255020
    	ADDU	R13, R14, R19	// 01cd9821
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Aug 08 12:17:12 GMT 2023
    - 12.4K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/s390x.s

    	ORW	(R1), R2              // 56201000
    	ORW	-1(R1), R2            // e3201fffff56
    	XOR	(R1), R2              // e32010000082
    	XORW	(R1), R2              // 57201000
    	XORW	-1(R1), R2            // e3201fffff57
    
    	// shift and rotate instructions
    	SRD	$4, R4, R7              // eb740004000c
    	SRD	R1, R4, R7              // eb741000000c
    	SRW	$4, R4, R7              // eb74000400de
    	SRW	R1, R4, R7              // eb74100000de
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Wed Nov 22 03:55:32 GMT 2023
    - 21.6K bytes
    - Viewed (0)
  6. src/cmd/asm/internal/asm/testdata/ppc64.s

    	// and accept the same constants.
    	MOVW $2147483648, R5            // 64058000
    	MOVWZ $-2147483648, R5          // 3ca08000
    
    	// TODO: These are preprocessed by the assembler into MOVD $const>>shift, R5; SLD $shift, R5.
    	//       This only captures the MOVD. Should the SLD be appended to the encoding by the test?
    	// Hex constant 0x20004000000
    	MOVD $2199090364416, R5         // 60058001
    	// Hex constant 0xFFFFFE0004000000
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Wed Apr 24 15:53:25 GMT 2024
    - 49K bytes
    - Viewed (0)
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