)

type rc4Test struct {
	key, keystream []byte
}

var golden = []rc4Test{
	// Test vectors from the original cypherpunk posting of ARC4:
	//   https://groups.google.com/group/sci.crypt/msg/10a300c9d21afca0?pli=1
	{
		[]byte{0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef},
		[]byte{0x74, 0x94, 0xc2, 0xe7, 0x10, 0x4b, 0x08, 0x79},
	},
	{
		[]byte{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},

	cfgCtlr.lockAndDigestConfigObjects(nil, nil)
	fci := config.InformerFactory.Flowcontrol().V1()
	pli := fci.PriorityLevelConfigurations()
	fsi := fci.FlowSchemas()
	cfgCtlr.plLister = pli.Lister()
	cfgCtlr.plInformerSynced = pli.Informer().HasSynced
	cfgCtlr.fsLister = fsi.Lister()
	cfgCtlr.fsInformerSynced = fsi.Informer().HasSynced
	pli.Informer().AddEventHandler(cache.ResourceEventHandlerFuncs{
		AddFunc: func(obj interface{}) {

				default:
					panic(fmt.Sprintf("wrong FP register: %v", inst))
				}
			}
		}
	}

	// Move addressing mode into opcode suffix.
	suffix := ""
	switch inst.Op &^ 15 {
	case PLD, PLI, PLD_W:
		if mem, ok := inst.Args[0].(Mem); ok {
			args[0], suffix = memOpTrans(mem)
		} else {
			panic(fmt.Sprintf("illegal instruction: %v", inst))
		}

		// the only valid mnemonic for paddi (R=1), In this case, RA must
		// always be 0.  Otherwise it is invalid.
		r := inst.Args[3].(Imm)
		ra := inst.Args[1].(Reg)
		str := opName
		if ra == R0 {
			name := []string{"pli", "pla"}
			str = fmt.Sprintf("%s %s,%s",
				name[r&1],
				gnuArg(&inst, 0, inst.Args[0], PC),
				gnuArg(&inst, 2, inst.Args[2], PC))
			startArg = 4
		} else {
			str = fmt.Sprintf("%s %s,%s,%s", opName,

	ADD $131073, R3              lis  r31, 2                paddi r3, r3, 131073
	                             addi r31, 1
	                             add  r3,r31,r3

	MOVD $131073, R3             lis  r3, 2                 pli r3, 131073
	                             addi r3, 1

	MOVD $mypackage·foo(SB), R3  addis r2, r3, ...          pla r3, ...
	                             addi  r3, r3, ...
*/

	{0xff70f000, 0xf450f000, 4, PLI, 0x0, instArgs{arg_mem_R_pm_imm12_offset}},                                    // PLI [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12
	{0xff700000, 0xf450f000, 3, PLI, 0x0, instArgs{arg_mem_R_pm_imm12_offset}},                                    // PLI [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12

	prf_type := (i >> 3) & (1<<2 - 1)
	prf_target := (i >> 1) & (1<<2 - 1)
	prf_policy := i & 1
	var result string

	switch prf_type {
	case 0:
		result = "PLD"
	case 1:
		result = "PLI"
	case 2:
		result = "PST"
	case 3:
		return fmt.Sprintf("#%#02x", uint8(i))
	}
	switch prf_target {
	case 0:
		result += "L1"
	case 1:
		result += "L2"
	case 2:
		result += "L3"

	// Hex constant 0xFFFFFFFF80000001
	MOVD $-2147483647, R5           // 3ca0800060a50001 or 0603800038a00001
	// Hex constant 0xFFFFFFFE00000002 (load of constant on < power10, pli on >= power10
	MOVD $-8589934590, R5           // 3ca00000e8a50000 or 0602000038a00002

	// For backwards compatibility, MOVW $const,Rx and MOVWZ $const,Rx assemble identically
	// and accept the same constants.

		isS32 := int64(int32(p.From.Offset)) == p.From.Offset
		isU32 := uint64(uint32(p.From.Offset)) == uint64(p.From.Offset)
		// If prefixed instructions are supported, a 34b signed constant can be generated by one pli instruction.
		isS34 := pfxEnabled && (p.From.Offset<<30)>>30 == p.From.Offset

		// Try converting MOVD $const,Rx into ADDIS/ORIS $s32>>16,R0,Rx
		switch {
		case isS32 && p.From.Offset&0xFFFF == 0 && p.From.Offset != 0: