case arg_mem_R_pm_imm12_offset:
		// Treat [<Rn>,#+/-<imm12>] like [<Rn>{,#+/-<imm12>}]{!}
		// by forcing P=1, W=0 (index=false, wback=false).
		return decodeArg(arg_mem_R_pm_imm12_W, x&^(1<<21)|1<<24)

	case arg_mem_R_pm_imm12_postindex:
		// Treat [<Rn>],#+/-<imm12> like [<Rn>{,#+/-<imm12>}]{!}
		// by forcing P=0, W=0 (postindex=true).
		return decodeArg(arg_mem_R_pm_imm12_W, x&^(1<<24|1<<21))

	{0x0ff00000, 0x03400000, 4, MOVT_EQ, 0x1c04, instArgs{arg_R_12, arg_imm_4at16_12at0}},                         // MOVT<c> <Rd>,#<imm12+4> cond:4|0|0|1|1|0|1|0|0|imm4:4|Rd:4|imm12:12
	{0x0ff00000, 0x03000000, 4, MOVW_EQ, 0x1c04, instArgs{arg_R_12, arg_imm_4at16_12at0}},                         // MOVW<c> <Rd>,#<imm12+4> cond:4|0|0|1|1|0|0|0|0|imm4:4|Rd:4|imm12:12

//     a W register encoded in Rm with a shift encoded in shift[23:22] and an amount
//     encoded in imm6[15:10] in the range [0,31].
//
// - arg_IAddSub:
//     An immediate for a add/sub instruction encoded in imm12[21:10] with an optional
//     left shift of 12 encoded in shift[23:22].
//
// - arg_Rt_31_1__W_0__X_1:
//     a W or X register encoded in Rt[4:0]. The width specifier is encoded in the field

	case arg_immediate_optional_0_65535_imm16:
		imm16 := (x >> 5) & (1<<16 - 1)
		return Imm_dcps(imm16)

	case arg_immediate_OptLSL_amount_16_0_16:
		imm16 := (x >> 5) & (1<<16 - 1)
		hw := (x >> 21) & (1<<2 - 1)
		shift := hw * 16
		if shift > 16 {
			return nil
		}
		return ImmShift{uint16(imm16), uint8(shift)}

	case arg_immediate_OptLSL_amount_16_0_48:
		imm16 := (x >> 5) & (1<<16 - 1)

{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|1|01:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|1|01:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 16-bit variant","Syntax":"LDR <Ht>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},

	}

	out.Write16(uint16(v))

	return true
}

// sign extend a 24-bit integer.
func signext24(x int64) int32 {
	return (int32(x) << 8) >> 8
}

// encode an immediate in ARM's imm12 format. copied from ../../../internal/obj/arm/asm5.go
func immrot(v uint32) uint32 {
	for i := 0; i < 16; i++ {
		if v&^0xff == 0 {
			return uint32(i<<8) | v | 1<<25
		}
		v = v<<2 | v>>30
	}
	return 0

	o1 |= uint32(p.From.Offset&0x1) << 17                     // IX
	o0 |= uint32((p.RestArgs[0].Addr.Offset>>16)&0xffff) << 0 // imm0
	o1 |= uint32(p.RestArgs[0].Addr.Offset&0xffff) << 0       // imm1
	out[1] = o1
	out[0] = o0
}

// xxspltiw XT,IMM32
func type_xxspltiw(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) {
	o0 := GenPfxOpcodes[p.As-AXXSPLTIW]
	o1 := GenOpcodes[p.As-AXXSETACCZ]

	X0:  "xmm0",
	X1:  "xmm1",
	X2:  "xmm2",
	X3:  "xmm3",
	X4:  "xmm4",
	X5:  "xmm5",
	X6:  "xmm6",
	X7:  "xmm7",
	X8:  "xmm8",
	X9:  "xmm9",
	X10: "xmm10",
	X11: "xmm11",
	X12: "xmm12",
	X13: "xmm13",
	X14: "xmm14",
	X15: "xmm15",

	// TODO: Maybe the constants are named wrong.
	SPB: "spl",
	BPB: "bpl",
	SIB: "sil",
	DIB: "dil",

	R8L:  "r8d",
	R9L:  "r9d",

	// LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]
	{0xffc00000, 0x29400000, LDP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_optional_imm7_4_signed}, nil},
	// LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm_2>}]
	{0xffc00000, 0xa9400000, LDP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_optional_imm7_8_signed}, nil},
	// LDPSW <Xt>, <Xt2>, [<Xn|SP>], #<imm_1>

	xArgDX           // arg DX
	xArgEAX          // arg EAX
	xArgEDX          // arg EDX
	xArgES           // arg ES
	xArgFS           // arg FS
	xArgGS           // arg GS
	xArgImm16        // arg imm16
	xArgImm32        // arg imm32
	xArgImm64        // arg imm64
	xArgImm8         // arg imm8
	xArgImm8u        // arg imm8 but record as unsigned
	xArgImm16u       // arg imm8 but record as unsigned
	xArgM            // arg m