"MULS",
	"MMULA",
	"MMULS",
	"WORD",
	"MULL",
	"MULAL",
	"MULLU",
	"MULALU",
	"BX",
	"BXRET",
	"DWORD",
	"LDREX",
	"STREX",
	"LDREXD",
	"STREXD",
	"DMB",
	"PLD",
	"CLZ",
	"REV",
	"REV16",
	"REVSH",
	"RBIT",
	"XTAB",
	"XTAH",
	"XTABU",
	"XTAHU",
	"BFX",
	"BFXU",
	"BFC",
	"BFI",
	"MULWT",
	"MULWB",
	"MULBB",
	"MULAWT",

	PDEPD R1, R2, R3                        // 7c231138
	PEXTD R1, R2, R3                        // 7c231178
	PLBZ 1234(R1), $0, R3                   // 06000000886104d260000000
	// Note, PLD crosses a 64B boundary, and a nop is inserted between PLBZ and PLD
	PLD 1234(R1), $0, R3                    // 04000000e46104d2
	PLFD 1234(R1), $0, F3                   // 06000000c86104d2
	PLFS 1234567890(R4), $0, F3             // 06004996c06402d2

	OP_LD            = 0xe8000000 // ld
	OP_PLA_PFX       = 0x06100000 // pla (prefix instruction word)
	OP_PLA_SFX       = 0x38000000 // pla (suffix instruction word)
	OP_PLD_PFX_PCREL = 0x04100000 // pld (prefix instruction word, R=1)
	OP_PLD_SFX       = 0xe4000000 // pld (suffix instruction word)
	OP_MFLR          = 0x7c0802a6 // mflr
	OP_MTLR          = 0x7c0803a6 // mtlr
	OP_MFCTR         = 0x7c0902a6 // mfctr
	OP_MTCTR         = 0x7c0903a6 // mtctr

	Go asm                       GOPPC64 <= power9          GOPPC64 >= power10
	MOVD mypackage·foo(SB), R3   addis r2, r3, ...          pld r3, ...
	                             ld    r3, r3, ...

	MOVD 131072(R3), R4          addis r31, r4, 2           pld r4, 131072(r3)
	                             ld    r4, 0(R3)

	ADD $131073, R3              lis  r31, 2                paddi r3, r3, 131073

//	{
//		$7.Type = obj.TYPE_REGREG2;
//		$7.Offset = int64($9);
//		outcode($1, $2, &$3, int32($5.Reg), &$7);
//	}
	MULAWT	R1, R2, R3, R4
//
// PLD
//
//	LTYPEPLD oreg
//	{
//		outcode($1, Always, &$2, 0, &nullgen);
//	}
	PLD	(R1)
	PLD	4(R1)

//
// RET
//
//	LTYPEA cond
//	{
//		outcode($1, $2, &nullgen, 0, &nullgen);
//	}
	BEQ	2(PC)
	RET

				default:
					panic(fmt.Sprintf("wrong FP register: %v", inst))
				}
			}
		}
	}

	// Move addressing mode into opcode suffix.
	suffix := ""
	switch inst.Op &^ 15 {
	case PLD, PLI, PLD_W:
		if mem, ok := inst.Args[0].(Mem); ok {
			args[0], suffix = memOpTrans(mem)
		} else {
			panic(fmt.Sprintf("illegal instruction: %v", inst))
		}

	{0xff7ff000, 0xf55ff000, 4, PLD, 0x0, instArgs{arg_label_pm_12}},                                              // PLD <label+/-12> 1|1|1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12
	{0xff3f0000, 0xf55ff000, 3, PLD, 0x0, instArgs{arg_label_pm_12}},                                              // PLD <label+/-12> 1|1|1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12

	MOVFW.P	F0, R9             // ERROR "invalid .P suffix"
	MOVWF.W	R3, F1             // ERROR "invalid .W suffix"
	MOVW.S	F0, R9             // ERROR "invalid .S suffix"
	MOVW.U	R3, F1             // ERROR "invalid .U suffix"
	PLD.S	4(R1)              // ERROR "invalid .S suffix"
	CLZ.S	R1, R2             // ERROR "invalid .S suffix"
	MULBB.S	R0, R1, R2         // ERROR "invalid .S suffix"
	MULA.W	R9, R6, R1, g      // ERROR "invalid .W suffix"

func (i Imm_prfop) String() string {
	prf_type := (i >> 3) & (1<<2 - 1)
	prf_target := (i >> 1) & (1<<2 - 1)
	prf_policy := i & 1
	var result string

	switch prf_type {
	case 0:
		result = "PLD"
	case 1:
		result = "PLI"
	case 2:
		result = "PST"
	case 3:
		return fmt.Sprintf("#%#02x", uint8(i))
	}
	switch prf_target {
	case 0:
		result += "L1"
	case 1:
		result += "L2"

	"PMXVBF16GER2NP",
	"PMXVBF16GER2NN",
	"PMXVBF16GER2",
	"PLXVP",
	"PLXV",
	"PLXSSP",
	"PLXSD",
	"PLWZ",
	"PLWA",
	"PLQ",
	"PLHZ",
	"PLHA",
	"PLFS",
	"PLFD",
	"PLD",
	"PLBZ",
	"PADDI",
}

var GenOpcodes = [...]uint32{
	0x7c030162, // AXXSETACCZ
	0x7c010162, // AXXMTACC
	0x7c000162, // AXXMFACC
	0xf0000768, // AXXGENPCVWM
	0xf000072a, // AXXGENPCVHM