i16test(a, b, -16384)
	}
}

func u16rand() uint16 {
	a := uint16(rand.Uint32())
	a >>= uint(rand.Intn(16))
	return a
}

func u16test(a, b, c uint16) {
	d := a / c
	if d != b {
		println("u16", a, b, c, d)
		panic("fail")
	}
}

func u16run() {
	var a, b uint16

	for i := 0; i < Count; i++ {
		a = u16rand()

		b = a / 1
		u16test(a, b, 1)
		b = a / 2

		i16test(a, b, -16384)
	}
}

func u16rand() uint16 {
	a := uint16(rand.Uint32())
	a >>= uint(rand.Intn(16))
	return a
}

func u16test(a, b, c uint16) {
	d := a % c
	if d != b {
		println("u16", a, b, c, d)
		panic("fail")
	}
}

func u16run() {
	var a, b uint16

	for i := 0; i < Count; i++ {
		a = u16rand()

		b = a % 1
		u16test(a, b, 1)
		b = a % 2

(SignExt8to(64|32|16) x) => (I64ShrS (I64Shl x (I64Const [56])) (I64Const [56]))
(ZeroExt32to64        x) => (I64And x (I64Const [0xffffffff]))
(ZeroExt16to(64|32)   x) => (I64And x (I64Const [0xffff]))
(ZeroExt8to(64|32|16) x) => (I64And x (I64Const [0xff]))

(Slicemask x) => (I64ShrS (I64Sub (I64Const [0]) x) (I64Const [63]))

// Lowering truncation

	"I32ShrS",
	"I32ShrU",
	"I32Rotl",
	"I32Rotr",
	"I64Clz",
	"I64Ctz",
	"I64Popcnt",
	"I64Add",
	"I64Sub",
	"I64Mul",
	"I64DivS",
	"I64DivU",
	"I64RemS",
	"I64RemU",
	"I64And",
	"I64Or",
	"I64Xor",
	"I64Shl",
	"I64ShrS",
	"I64ShrU",
	"I64Rotl",
	"I64Rotr",
	"F32Abs",
	"F32Neg",
	"F32Ceil",
	"F32Floor",
	"F32Trunc",
	"F32Nearest",
	"F32Sqrt",

		{name: "I64RemU", asm: "I64RemU", argLength: 2, reg: gp21, typ: "Int64"},                  // arg0 % arg1 (unsigned)
		{name: "I64And", asm: "I64And", argLength: 2, reg: gp21, typ: "Int64"},                    // arg0 & arg1
		{name: "I64Or", asm: "I64Or", argLength: 2, reg: gp21, typ: "Int64"},                      // arg0 | arg1

		y := auxIntToInt64(v_1.AuxInt)
		v.reset(OpWasmI64Const)
		v.AuxInt = int64ToAuxInt(x & y)
		return true
	}
	// match: (I64And (I64Const [x]) y)
	// cond: y.Op != OpWasmI64Const
	// result: (I64And y (I64Const [x]))
	for {
		if v_0.Op != OpWasmI64Const {
			break
		}
		x := auxIntToInt64(v_0.AuxInt)
		y := v_1
		if !(y.Op != OpWasmI64Const) {
			break
		}
		v.reset(OpWasmI64And)

			},
			outputs: []outputInfo{
				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:   "I64And",
		argLen: 2,
		asm:    wasm.AI64And,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP