"I64Mul",
	"I64DivS",
	"I64DivU",
	"I64RemS",
	"I64RemU",
	"I64And",
	"I64Or",
	"I64Xor",
	"I64Shl",
	"I64ShrS",
	"I64ShrU",
	"I64Rotl",
	"I64Rotr",
	"F32Abs",
	"F32Neg",
	"F32Ceil",
	"F32Floor",
	"F32Trunc",
	"F32Nearest",
	"F32Sqrt",
	"F32Add",
	"F32Sub",
	"F32Mul",
	"F32Div",
	"F32Min",
	"F32Max",
	"F32Copysign",
	"F64Abs",
	"F64Neg",

    <I16Neg>  -6703  </I16Neg>
    <I32>  266703  </I32>
    <I32Neg>  -266703  </I32Neg>
    <I64>  266703  </I64>
    <I64Neg>  -266703  </I64Neg>
    <UI>   266703   </UI>
    <UI8>  112  </UI8>
    <UI16>  6703  </UI16>
    <UI32>  266703  </UI32>
    <UI64>  266703  </UI64>
    <F32>  266.703  </F32>
    <F32Neg>  -266.703  </F32Neg>
    <F64>  266.703  </F64>
    <F64Neg>  -266.703  </F64Neg>

		{name: "I64ShrU", asm: "I64ShrU", argLength: 2, reg: gp21, typ: "Int64"},                  // arg0 >> (arg1 % 64) (unsigned)

		{name: "F32Neg", asm: "F32Neg", argLength: 1, reg: fp32_11, typ: "Float32"}, // -arg0
		{name: "F32Add", asm: "F32Add", argLength: 2, reg: fp32_21, typ: "Float32"}, // arg0 + arg1

			},
			outputs: []outputInfo{
				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:   "F32Neg",
		argLen: 1,
		asm:    wasm.AF32Neg,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{