(Abs ...) => (F64Abs ...)
(Copysign ...) => (F64Copysign ...)

(Sqrt32 ...) => (F32Sqrt ...)

(Ctz64 ...) => (I64Ctz ...)
(Ctz32 x) => (I64Ctz (I64Or x (I64Const [0x100000000])))
(Ctz16 x) => (I64Ctz (I64Or x (I64Const [0x10000])))
(Ctz8  x) => (I64Ctz (I64Or x (I64Const [0x100])))

(Ctz(64|32|16|8)NonZero ...) => (I64Ctz ...)

(BitLen64 x) => (I64Sub (I64Const [64]) (I64Clz x))

	"I32ShrU",
	"I32Rotl",
	"I32Rotr",
	"I64Clz",
	"I64Ctz",
	"I64Popcnt",
	"I64Add",
	"I64Sub",
	"I64Mul",
	"I64DivS",
	"I64DivU",
	"I64RemS",
	"I64RemU",
	"I64And",
	"I64Or",
	"I64Xor",
	"I64Shl",
	"I64ShrS",
	"I64ShrU",
	"I64Rotl",
	"I64Rotr",
	"F32Abs",
	"F32Neg",
	"F32Ceil",
	"F32Floor",
	"F32Trunc",
	"F32Nearest",
	"F32Sqrt",
	"F32Add",

		{name: "I64And", asm: "I64And", argLength: 2, reg: gp21, typ: "Int64"},                    // arg0 & arg1
		{name: "I64Or", asm: "I64Or", argLength: 2, reg: gp21, typ: "Int64"},                      // arg0 | arg1
		{name: "I64Xor", asm: "I64Xor", argLength: 2, reg: gp21, typ: "Int64"},                    // arg0 ^ arg1

		y := auxIntToInt64(v_1.AuxInt)
		v.reset(OpWasmI64Const)
		v.AuxInt = int64ToAuxInt(x | y)
		return true
	}
	// match: (I64Or (I64Const [x]) y)
	// cond: y.Op != OpWasmI64Const
	// result: (I64Or y (I64Const [x]))
	for {
		if v_0.Op != OpWasmI64Const {
			break
		}
		x := auxIntToInt64(v_0.AuxInt)
		y := v_1
		if !(y.Op != OpWasmI64Const) {
			break
		}
		v.reset(OpWasmI64Or)

			},
			outputs: []outputInfo{
				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:   "I64Or",
		argLen: 2,
		asm:    wasm.AI64Or,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP