(SignExt16to(64|32)   x) && buildcfg.GOWASM.SignExt => (I64Extend16S x)
(SignExt32to64        x) => (I64ShrS (I64Shl x (I64Const [32])) (I64Const [32]))
(SignExt16to(64|32)   x) => (I64ShrS (I64Shl x (I64Const [48])) (I64Const [48]))
(SignExt8to(64|32|16) x) => (I64ShrS (I64Shl x (I64Const [56])) (I64Const [56]))
(ZeroExt32to64        x) => (I64And x (I64Const [0xffffffff]))

	"I32Rotr",
	"I64Clz",
	"I64Ctz",
	"I64Popcnt",
	"I64Add",
	"I64Sub",
	"I64Mul",
	"I64DivS",
	"I64DivU",
	"I64RemS",
	"I64RemU",
	"I64And",
	"I64Or",
	"I64Xor",
	"I64Shl",
	"I64ShrS",
	"I64ShrU",
	"I64Rotl",
	"I64Rotr",
	"F32Abs",
	"F32Neg",
	"F32Ceil",
	"F32Floor",
	"F32Trunc",
	"F32Nearest",
	"F32Sqrt",
	"F32Add",
	"F32Sub",
	"F32Mul",

		{name: "I64Or", asm: "I64Or", argLength: 2, reg: gp21, typ: "Int64"},                      // arg0 | arg1
		{name: "I64Xor", asm: "I64Xor", argLength: 2, reg: gp21, typ: "Int64"},                    // arg0 ^ arg1
		{name: "I64Shl", asm: "I64Shl", argLength: 2, reg: gp21, typ: "Int64"},                    // arg0 << (arg1 % 64)
		{name: "I64ShrS", asm: "I64ShrS", argLength: 2, reg: gp21, typ: "Int64"},                  // arg0 >> (arg1 % 64) (signed)

	// match: (Lsh64x64 x y)
	// cond: shiftIsBounded(v)
	// result: (I64Shl x y)
	for {
		x := v_0
		y := v_1
		if !(shiftIsBounded(v)) {
			break
		}
		v.reset(OpWasmI64Shl)
		v.AddArg2(x, y)
		return true
	}
	// match: (Lsh64x64 x (I64Const [c]))
	// cond: uint64(c) < 64
	// result: (I64Shl x (I64Const [c]))
	for {
		x := v_0
		if v_1.Op != OpWasmI64Const {

			},
			outputs: []outputInfo{
				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:   "I64Shl",
		argLen: 2,
		asm:    wasm.AI64Shl,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP